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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2015)
Search Results: Keywords 'from:2015-04-16 to:2015-04-16'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2015-04-16 13:00 |
Nagano | [Invited Lecture]
20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii (Renesas)  ICD2015-1 |
[more] | ICD2015-1 pp.1-4 |
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| ICD | 2015-04-16 13:25 |
Nagano | [Invited Lecture]
A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2 |
[more] | ICD2015-2 pp.5-8 |
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| ICD | 2015-04-16 13:50 |
Nagano | [Invited Lecture]
40 nm Dual-port and Two-port SRAMs for Automotive MCU Applications under the Wide Temperature Range of -40 to 170℃ with Test Screening Against Write Disturb Issues Yoshisato Yokoyama, Yuichiro Ishii, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi (Renesas Electronics), Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba (Renesas Semiconductor Manufacturing Corporation), Koji Nii (Renesas Electronics) ICD2015-3 |
(To be available after the conference date) [more] | ICD2015-3 pp.9-14 |
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| ICD | 2015-04-16 14:25 |
Nagano | [Invited Talk]
A 28nm Embedded SG-MONOS Flash Macro for Automotive Achieving 200MHz Read Operation and 2.0MB/s Write Throughput at Tj of 170℃ Makoto Muneyasu, Yasuhiko Taito, Masaya Nakano, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi (Renesas) ICD2015-4 |
First-ever 28nm embedded SG-MONOS flash macros are presented to realize aggressive device scaling with improved reliabil... [more] | ICD2015-4 pp.15-19 |
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| ICD | 2015-04-16 15:15 |
Nagano | [Invited Talk]
Reliability enhancement techniques of TLC NAND Flash Solid-State Drives (SSDs) for archive and enterprise applications Shogo Hachiya, Shuhei Tanakamaru, Tsukasa Tokutomi, Masafumi Doi, Yuta Kitamura, Senju Yamazaki, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2015-5 |
[more] | ICD2015-5 pp.21-26 |
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| ICD | 2015-04-16 16:05 |
Nagano | [Invited Lecture]
A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology Mario Sako, Takao Nakajima, Junpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Yoshinao Suzuki, Yoshihisa Watanabe (Toshiba), Ryuji Yamashita (SanDisk) ICD2015-6 |
A 75mm2 low power 64Gb MLC NAND flash memory capable of 30MB/s program throughput and 533MB/s data transfer rate at 1.8V... [more] | ICD2015-6 pp.27-30 |
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| ICD | 2015-04-16 16:40 |
Nagano | [Panel Discussion]
Advanced semiconductor memories in cloud computing and high-performance computing Koji Nii (Renesas Electronics), Kousuke Miyaji (Shinshu Univ.), Ryousei Takano (AIST), Kensei Takagi, Toru Miwa (SanDisk) ICD2015-7 |
(To be available after the conference date) [more] | ICD2015-7 p.31 |
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| ICD | 2015-04-17 10:00 |
Nagano | [Invited Talk]
GexTe1-x/Sb2Te3 Topological switching random access memory (TRAM) Norikatsu Takaura (LEAP) ICD2015-8 |
[more] | ICD2015-8 pp.33-37 |
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| ICD | 2015-04-17 10:50 |
Nagano | [Invited Talk]
A 128kb 4bit/cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto (SEL), Masahiro Fujita (The Univ. of Tokyo), Jun Koyama, Shunpei Yamazaki (SEL) ICD2015-9 |
A 128kbit 4bit/cell memory is achieved by a nonvolatile oxide semiconductor RAM test chip with a c-axis aligned crystall... [more] | ICD2015-9 pp.39-44 |
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| ICD | 2015-04-17 12:40 |
Nagano | [Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] | ICD2015-10 pp.45-50 |
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| ICD | 2015-04-17 13:30 |
Nagano | [Invited Lecture]
A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori (ROHM), Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2015-11 |
A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in ... [more] |
ICD2015-11 pp.51-55 |
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| ICD | 2015-04-17 13:55 |
Nagano | [Tutorial Lecture]
Nonvolatile Logic-in-Memory Architecture and Its Applications to Low-Power VLSI System Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa (Tohoku Univ.), Tadahiko Sugibayashi (NEC), Shoji Ikeda, Tetsuo Endoh, Hideo Ohno (Tohoku Univ.) ICD2015-12 |
[more] | ICD2015-12 pp.57-61 |
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| ICD | 2015-04-17 14:55 |
Nagano | [Invited Talk]
An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi) ICD2015-13 |
A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, ... [more] | ICD2015-13 pp.63-68 |
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| ICD | 2015-04-17 15:45 |
Nagano | [Invited Talk]
Non-Contact Memory Interface using Transmission Line Coupler Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda (Keio Univ.) ICD2015-14 |
[more] | ICD2015-14 pp.69-74 |
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| ICD | 2015-04-17 16:35 |
Nagano | [Invited Lecture]
An Inductive-Coupling Interface Using Partially Overlapping Coil for WIO2 and Beyond Yasuhiro Take, Tadahiro Kuroda (Keio Univ.) ICD2015-15 |
[more] | ICD2015-15 pp.75-79 |
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