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Technical Committee on Hardware Security (HWS) (Searched in: 2020)
Search Results: Keywords 'from:2021-03-03 to:2021-03-03'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD [detail] | 2021-03-03 10:00 |
Online | Online | Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing Yoshinori Ono, Kimiyoshi Usami (SIT)  VLD2020-67 HWS2020-42 |
On-chip learning is gaining attention in edge devices. In addition, a magnetic RAM (MRAM) is a promising memory technolo... [more] | VLD2020-67 HWS2020-42 pp.1-6 |
| HWS, VLD [detail] | 2021-03-03 10:25 |
Online | Online | Evaluation on Approximate Multiplier for CNN Calculation Yuechuan Zhang, Masahiro Fujita, Takashi Matsumoto (UTokyo) VLD2020-68 HWS2020-43 |
Improving the accuracy of a convolutional neural network (CNN) typically requires larger hardware with more energy consu... [more] | VLD2020-68 HWS2020-43 pp.7-12 |
| HWS, VLD [detail] | 2021-03-03 10:50 |
Online | Online | A performance and resources estimation of AI Inference circuit on FPGAs Ryo Yamamoto, Iwagawa Hidetoshi, Yoshihiro Ogawa (MELCO) VLD2020-69 HWS2020-44 |
[more] | VLD2020-69 HWS2020-44 pp.13-17 |
| HWS, VLD [detail] | 2021-03-03 11:15 |
Online | Online | The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) VLD2020-70 HWS2020-45 |
Quantization is used to speed up execution time and save power when runnning Deep neural networks (DNNs) on edge devices... [more] | VLD2020-70 HWS2020-45 pp.18-23 |
| HWS, VLD [detail] | 2021-03-03 13:00 |
Online | Online | [Memorial Lecture]
Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) VLD2020-71 HWS2020-46 |
There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally inte... [more] | VLD2020-71 HWS2020-46 pp.24-29 |
| HWS, VLD [detail] | 2021-03-03 13:25 |
Online | Online | [Memorial Lecture]
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.) VLD2020-72 HWS2020-47 |
This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with a... [more] | VLD2020-72 HWS2020-47 p.30 |
| HWS, VLD [detail] | 2021-03-03 13:50 |
Online | Online | [Memorial Lecture]
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita (Ritsumeikan University) VLD2020-73 HWS2020-48 |
We usually use {it Mixed-Polarity Multiple-Control Toffoli (MPMCT)} gates to realize large control logic functions for q... [more] | VLD2020-73 HWS2020-48 p.31 |
| HWS, VLD [detail] | 2021-03-03 14:30 |
Online | Online | Measurement of Voltage-variation-tolerant Temperature Sensor for Standard CMOS Chip with On-chip Solar Cell Shuto Murohara, Tatsuya Banno, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2020-74 HWS2020-49 |
Aiming at realizing a CMOS-process-compatible external-component-free SoC with an on-chip solar cell and a temperature s... [more] | VLD2020-74 HWS2020-49 pp.32-37 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-03 15:20 |
Online | Online | Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2020-76 HWS2020-51 |
(To be available after the conference date) [more] | VLD2020-76 HWS2020-51 pp.44-49 |
| HWS, VLD [detail] | 2021-03-03 16:00 |
Online | Online | Highly Efficient Simulation Method to Find Hardware Trojans Hidden in Semiconductor Chips Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Masaru Mashiba, Takuji Miki, Makoto Nagata (Kobe Univ.) VLD2020-77 HWS2020-52 |
[more] | VLD2020-77 HWS2020-52 pp.50-54 |
| HWS, VLD [detail] | 2021-03-03 16:25 |
Online | Online | Counteracting Chip Transplantation Attack using Hologram on Epoxy Covering Takashi Sudo, Takeshi Sugawara (UEC) VLD2020-78 HWS2020-53 |
[more] | VLD2020-78 HWS2020-53 pp.55-60 |
| HWS, VLD [detail] | 2021-03-04 09:30 |
Online | Online | Design space exploration on low energy embedded multi-core processors Sayuri Onagi, Yuko Hara (Tokyo Tech) VLD2020-79 HWS2020-54 |
Nowadays, edge computing has been sought by increasing stream data and demand for real time processing so that distribut... [more] | VLD2020-79 HWS2020-54 pp.61-66 |
| HWS, VLD [detail] | 2021-03-04 09:55 |
Online | Online | High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] | VLD2020-80 HWS2020-55 pp.67-72 |
| HWS, VLD [detail] | 2021-03-04 10:20 |
Online | Online | A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI Tomohiro Noguchi, Hindawi Omran, Mineo Kaneko (JAIST) VLD2020-81 HWS2020-56 |
[more] | VLD2020-81 HWS2020-56 pp.73-78 |
| HWS, VLD [detail] | 2021-03-04 10:45 |
Online | Online | [Special Talk]
Efficient VLSI Layout Data Structures and Algorithms
-- a Brief Tutorial -- Shmuel Wimer (Bar-Ilan University) |
Moore's Law which stopped delivering CMOS device speedup for already a decade is still delivering and will do so for the... [more] | |
| HWS, VLD [detail] | 2021-03-04 13:00 |
Online | Online | Design of Area-Efficient Response Generator for CMOS Image Sensor PUF Masanori Aoki, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2020-82 HWS2020-57 |
(To be available after the conference date) [more] | VLD2020-82 HWS2020-57 pp.79-84 |
| HWS, VLD [detail] | 2021-03-04 13:25 |
Online | Online | A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58 |
In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The lat... [more] | VLD2020-83 HWS2020-58 pp.85-90 |
| HWS, VLD [detail] | 2021-03-04 13:50 |
Online | Online | Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.) VLD2020-84 HWS2020-59 |
This paper presents a new AES S-Box hardware design based on the optimization of linear mappings by combining multiplica... [more] | VLD2020-84 HWS2020-59 pp.91-96 |
| HWS, VLD [detail] | 2021-03-04 14:15 |
Online | Online | Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) VLD2020-85 HWS2020-60 |
Practicality of IoT systems requires the efficiency and speed of crypto processing in edge nodes and remote servers. So ... [more] | VLD2020-85 HWS2020-60 pp.97-101 |
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