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Technical Committee on Dependable Computing (DC)  (Searched in: 2010)

Search Results: Keywords 'from:2011-02-14 to:2011-02-14'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2011-02-14
10:00		 Tokyo Kikai-Shinko-Kaikan Bldg. The development of the DDR3 memory module tester used on memory test processor
Takeshi Asakawa, Satoshi Matsuno (Tokai Univ.), Hidekazu Tsuchiya (Hitachi), Tatsuya Seki, Shinichi Kmazawa (Techinica) DC2010-59		 The testing for the memory module is necessary to warrant the quality in the memory module manufacturer. However, there ... [more] DC2010-59
pp.1-6
DC 2011-02-14
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60		 Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] DC2010-60
pp.7-12
DC 2011-02-14
11:00		 Tokyo Kikai-Shinko-Kaikan Bldg. An Analysis of Critical Paths for Field Testing with Process Variation Consideration
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61		 Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] DC2010-61
pp.13-19
DC 2011-02-14
11:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Variation Aware Test Methodology Based on Statistical Static Timing Analysis
Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62		 The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to proces... [more] DC2010-62
pp.21-26
DC 2011-02-14
11:50		 Tokyo Kikai-Shinko-Kaikan Bldg. A Pattern Generation Method to Uniform Initial Temperature of Test Application
Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-63		 Circuit failure prediction is essential to ensure product quality and in-field reliability. The basic principle of circu... [more] DC2010-63
pp.27-32
DC 2011-02-14
13:45		 Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Generation for Highly Accurate Delay Testing
Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64		 We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] DC2010-64
pp.33-38
DC 2011-02-14
14:10		 Tokyo Kikai-Shinko-Kaikan Bldg. A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65		 Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] DC2010-65
pp.39-44
DC 2011-02-14
14:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Selection for Defect-Aware Test
Hiroshi Furutani, Takao Sakai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2010-66		 With shrinking of LSIs, the diversification of defective mode due to defects becomes a critical issue. Therefore, test p... [more] DC2010-66
pp.45-50
DC 2011-02-14
15:15		 Tokyo Kikai-Shinko-Kaikan Bldg. An Extended 2-D FPGA Array for CIP Circuit
Jiang Li, Kenichi Takahashi, Hakaru Tamukoh, Masatoshi Sekine (TUAT) DC2010-67		 The general-purpose processer is used in the most of HPC computer. In recent years，special-purpose processer used in HPC... [more] DC2010-67
pp.51-56
DC 2011-02-14
15:40		 Tokyo Kikai-Shinko-Kaikan Bldg. Dual Edge Triggered Flip-Flops for Blocking Noise Pulses on Data Signal Lines
Yukiya Miura (Tokyo Metropolitan Univ.) DC2010-68		 This paper proposes a new flip-flop design, a dual edge triggered flip-flops, for dependable design taking into account ... [more] DC2010-68
pp.57-62
DC 2011-02-14
16:05		 Tokyo Kikai-Shinko-Kaikan Bldg. Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-69		 In this study we evaluate the effectiveness of a reconfigurable on-chip debug circuit, in terms of hardware overhead and... [more] DC2010-69
pp.63-68
 Results 1 - 11 of 11  /   
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