| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Technical Committee on Dependable Computing (DC) (Searched in: 2007)
Search Results: Keywords 'from:2008-02-08 to:2008-02-08'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2008-02-08 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | ESD/Latch up Failure Analysis of CMOS LSI
-- Failure Mode Analysis with Atutual Data -- Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)  DC2007-67 |
As the CMOS LSI advances, ESD/Latch-up problem is becoming more serious problem as a weakness of CMOS LSI structure. Thi... [more] | DC2007-67 pp.1-5 |
| DC | 2008-02-08 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fault Diagnosis for Dyinamic Open Faults with Considering Adjacent Lines Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Syuhei Kadoyama, Tetsuya Watanabe, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Kouji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2007-68 |
In modern manufacturing technologies with the shrinking of manufacturing process, LSIs may have several metal interconne... [more] | DC2007-68 pp.7-12 |
| DC | 2008-02-08 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Diagnostic Test Generation for Transition Faults Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Toru Kikkawa, Yuzo Takamatsu (Ehime Univ.) DC2007-69 |
In modern manufacturing technologies with the shrinking of manufacturing process, LSIs may have several metal intercon... [more] |
DC2007-69 pp.13-18 |
| DC | 2008-02-08 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Generation Method for Full Scan Circuit Using Multi Cycle Capture Test Yusho Omori, Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Koji Yamazaki (Meiji Univ.) DC2007-70 |
Currently, scan testing is one of the most popular test methods for VLSIs. In this testing, only information of the circ... [more] | DC2007-70 pp.19-24 |
| DC | 2008-02-08 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A variable n-detection test generation method to increase fault sensitization coverage and evaluation of its test quality Takeshi Tomita, Toshinori Hosokawa (Nihon University), Koji Yamazaki (Meiji University) DC2007-71 |
N-deteciton test generation is known as one of the generation method of high-quality test set. However, many tests which... [more] | DC2007-71 pp.25-31 |
| DC | 2008-02-08 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Test Power Reduction for Scan-Based Hybrid BIST Akifumi Suto, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2007-72 |
[more] | DC2007-72 pp.33-38 |
| DC | 2008-02-08 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Secure Scan Design Based on Ballanced Structure Muneo Hasegawa, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-73 |
In this paper, we propose a secure scan design which protects scan-based side channel attacks to the circuits containing... [more] | DC2007-73 pp.39-44 |
| DC | 2008-02-08 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fault Secure Property for Soft Error on FPGA Using Two-Rail Logic Takehiro Miura, Kazuteru Namba, Hideo Ito (Chiba Univ.) DC2007-74 |
In recent high-density VLSIs, soft errors frequently occur. Soft errors cause improper operation of systems. Recently, r... [more] | DC2007-74 pp.45-50 |
| DC | 2008-02-08 13:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Generation for Two-phase Dual-rail Circuits Based on Time Expansion of C-elements Masaaki Takegahara, Tsuyoshi Iwagaki, Mineo Kaneko (JAIST) |
[more] | |
| DC | 2008-02-08 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Synthesis of Fault Secure Datapaths with DFG Restructuring Hirotaka Shiomichi (Hiroshima City Univ.), Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City) DC2007-75 |
This paper considers a method for synthesizing fault secure datapaths by concurrent error detection. Defining the comp... [more] |
DC2007-75 pp.51-56 |
| DC | 2008-02-08 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation of encryption LSI testability against scan based attack Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ.) DC2007-76 |
Recently, an encryption LSI is embedded in a variety of digital products for security and copyright protection. Most L... [more] |
DC2007-76 pp.57-62 |
| DC | 2008-02-08 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | RTL False Path Identification Using High Level Synthesis Information Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-77 |
This paper proposes a method of RTL false path identification using high level synthesis information. By using the false... [more] | DC2007-77 pp.63-68 |
| DC | 2008-02-08 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint Ryoichi Inoue, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) DC2007-78 |
We proposed a fault-independent test generation method for logical fault testing of state-observable FSMs and a fault-de... [more] | DC2007-78 pp.69-76 |
| DC | 2008-02-08 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Comparison of exact solutions and greedy solutions in static test compaction Kei Yagisawa, Koji Yamazaki (Meiji Univ.), Toshinori Hosokawa (Nihon Univ.), Hisao Tamaki (Meiji Univ.) DC2007-79 |
In this paper, we formulate static test compaction using don't cares as a minimum clique cover problem and a vertex colo... [more] | DC2007-79 pp.77-82 |
| DC | 2008-02-08 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Current dissipation of Test pattern generators using ATPG vectors Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa (Tokai univ.) DC2007-80 |
Recently, the operating speed of LSI is more fast and the scale of LSI is more larger. These induce increasing the dissi... [more] | DC2007-80 pp.83-88 |
| DC | 2008-02-08 16:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Testing of RF Transmitter Considering Component Variation Tatsuro Endo, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2007-81 |
As the higher integration level and more complexity on RF ICs, testing of them has been becoming a important problem. RF... [more] | DC2007-81 pp.89-94 |
| DC | 2008-02-08 16:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fault Diagnosis of Analog Circuits by Using Multiple Transistors and Data Samplings Jiro Kato, Yukiya Miura (Tokyo Metropolitan Univ.) DC2007-82 |
In this paper, we propose two methods for diagnosing analog circuits by using multiple transistors and data samplings, w... [more] | DC2007-82 pp.95-100 |
| DC | 2008-02-08 17:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Self-Correction Method for Periodic Signals Yukiya Miura (Tokyo Metropolitan Univ.) DC2007-83 |
The change of a periodic signal width induced by a noise causes malfunction of synchronous digital systems. In order to ... [more] | DC2007-83 pp.101-106 |
[Return to Top Page]