IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on Dependable Computing (DC)  (Searched in: 2020)

Search Results: Keywords 'from:2020-10-12 to:2020-10-12'

[Go to Official DC Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
10:15
Online Online Replay overhead reduction in Embedded Non-stop OS that using Trace Buffer
Nao Sugiyama, Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.) CPSY2020-17 DC2020-17
In an embedded system environment, it is necessary to keep safe the system from some problem. In particular, power suppl... [more] CPSY2020-17 DC2020-17
pp.1-6
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
11:30
Online Online Taint tracking system in container-based virtualization environment
Ayato Tachibana, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2020-18 DC2020-18
Decentralized Information Flow Control (DIFC) is an access control system which protect information without system opera... [more] CPSY2020-18 DC2020-18
pp.7-11
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
14:10
Online Online Soft error tolerant SR latch using C-element
Ibuki Nakata, Kazuteru Namba (Chiba Univ) CPSY2020-19 DC2020-19
VLSI systems have become downsized, high integrated and low-power. As a result, the incidence of soft errors is increasi... [more] CPSY2020-19 DC2020-19
pp.12-15
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
15:20
Online Online Note on CNN-Based Defect Location Estimation on LSI Layouts
Yoshikazu Nagamura (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metro. Univ.) CPSY2020-20 DC2020-20
 [more] CPSY2020-20 DC2020-20
pp.16-21
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
15:50
Online Online A Case for FPGA Implementation of ODE-Based Neural Networks
Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.) CPSY2020-21 DC2020-21
(To be available after the conference date) [more] CPSY2020-21 DC2020-21
pp.22-27
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan