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Technical Committee on Dependable Computing (DC)  (Searched in: 2018)

Search Results: Keywords 'from:2019-02-27 to:2019-02-27'

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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2019-02-27
09:00
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Target Fault Selection for 2-Pattern Test Generation Considering Critical Area
Naoya Uchiyama, Masayuki Arai (Nihon Univ.) DC2018-71
 [more] DC2018-71
pp.1-5
DC 2019-02-27
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. Variational Autoencoder-Based Efficient Test Escape Detection
Michihiro Shintani (NAIST), Kouichi Kumaki (Renesas Electronics Corporation), Michiko Inoue (NAIST) DC2018-72
 [more] DC2018-72
pp.7-12
DC 2019-02-27
09:50
Tokyo Kikai-Shinko-Kaikan Bldg. A Low Capture Power Oriented X-Identification Method Mimicking Fault Propagation Paths of Capture Safe Test Vectors
Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ) DC2018-73
Low power oriented don't care (X) identification and X filling methods have been proposed to reduce the numbers of captu... [more] DC2018-73
pp.13-18
DC 2019-02-27
10:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of the hotspot distribution in the LSI
Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] DC2018-74
pp.19-24
DC 2019-02-27
10:55
Tokyo Kikai-Shinko-Kaikan Bldg. Efficient Challenge-Response Pairs Generation and Evaluation for PUF Circuit Using BIST Circuit During Manufacturing Test
Tomoki Mino, Shintani Michihiro, Michiko Inoue (NAIST) DC2018-75
Recently, counterfeited ICs have become a big problem for semiconductor supply chains. One of the countermeasures for th... [more] DC2018-75
pp.25-30
DC 2019-02-27
11:20
Tokyo Kikai-Shinko-Kaikan Bldg. A built-in self-diagnosis mechanism based on self-generation of expected signatures
Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.), Hiroshi Takahashi (Ehime Univ.) DC2018-76
 [more] DC2018-76
pp.31-36
DC 2019-02-27
11:45
Tokyo Kikai-Shinko-Kaikan Bldg. An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling
Foisal Ahmed, Michihiro Shintani, Michiko Inoue (NAIST) DC2018-77
Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their perfo... [more] DC2018-77
pp.37-42
DC 2019-02-27
13:40
Tokyo Kikai-Shinko-Kaikan Bldg. State Assignment Method to Improve Transition Fault Coverage for Datapath
Masayoshi Yoshimura (Kyoto Sangyo Univ.), Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.) DC2018-78
Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication a... [more] DC2018-78
pp.43-48
DC 2019-02-27
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing
Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] DC2018-79
pp.49-54
DC 2019-02-27
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. A Compaction Method for Test Sensitization State in Controllers
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] DC2018-80
pp.55-60
DC 2019-02-27
15:10
Tokyo Kikai-Shinko-Kaikan Bldg. State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines
Yuki Maeda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2018-81
Stochastic Computing (SC) has attractive characteristics, compared with deterministic (or general binary) computing, suc... [more] DC2018-81
pp.61-66
DC 2019-02-27
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2018-82
With the scaling down and low-power operation of VLSI circuits, influence on circuit behavior by power supply noise such... [more] DC2018-82
pp.67-72
DC 2019-02-27
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. DC2018-83 (To be available after the conference date) [more] DC2018-83
pp.73-76
DC 2019-02-27
16:25
Tokyo Kikai-Shinko-Kaikan Bldg. Reliability evaluation of the optical navigation electronics of HAYABUSA2 -- Onboard demonstration of a high reliability system with limited resources --
Hiroki Hihara (NECSpace/NEC), Junpei Sano (NECSpace), Tetsuya Masuda (NEC), Hisashi Otake, Tatsuaki Okada, Naoko Ogawa, Yuichi Tsuda (JAXA) DC2018-84
The optical navigation camera digital electronics of HAYABUSA2 asteroid probe was developed to fulfill the reliability a... [more] DC2018-84
pp.77-82
 Results 1 - 14 of 14  /   
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