Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC, CPSY |
2015-04-17 09:00 |
Tokyo |
|
Redundant Configuration on FPGA with Rejuvenation for Real Time Applications Aromhack Saysanasongkham, Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2015-1 DC2015-1 |
SRAM-based FPGAs are susceptible to SEU which is induced by high energy particles or radiation. An SEU can corrupt the s... [more] |
CPSY2015-1 DC2015-1 pp.1-6 |
DC, CPSY |
2015-04-17 09:25 |
Tokyo |
|
Off-loading to PEACH2 of Gravitational Calculation Chiharu Tsuruta, Takuya Kuhara (Keio univ.), Miki Yohei (Univ. of Tsukuba), Hideharu Amano (Keio univ.) CPSY2015-2 DC2015-2 |
On-the-fly computation in the field-programmable gate array (FPGA)
used for the switching hub is one potential way to ... [more] |
CPSY2015-2 DC2015-2 pp.7-12 |
DC, CPSY |
2015-04-17 09:50 |
Tokyo |
|
A Proposal of Time-Lag-Less n-Fault-Tolerant Control System Hitoshi Iwai CPSY2015-3 DC2015-3 |
In a conventional multi-modular majority voting redundancy for real-time hazard control the first processing step is tha... [more] |
CPSY2015-3 DC2015-3 pp.13-18 |
DC, CPSY |
2015-04-17 10:25 |
Tokyo |
|
3D Shared Bus Architecture Using Inductive-Coupling Interconnect Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano (Keio Univ.) CPSY2015-4 DC2015-4 |
(To be available after the conference date) [more] |
CPSY2015-4 DC2015-4 pp.19-24 |
DC, CPSY |
2015-04-17 10:50 |
Tokyo |
|
Design and Implementation of FPGA-based Sorting Accelerator Ryohei Kobayashi, Kenji Kise (Tokyo Tech) CPSY2015-5 DC2015-5 |
Sorting is an extremely important computation kernel that has been tried to be accelerated in a lot of fields, such as d... [more] |
CPSY2015-5 DC2015-5 pp.25-30 |
DC, CPSY |
2015-04-17 11:15 |
Tokyo |
|
An IP-NoC Translator for Connecting NoCs and Internet Naoaki Kashiwagi, Hiroki Matsutani (Keio Univ.) CPSY2015-6 DC2015-6 |
[more] |
CPSY2015-6 DC2015-6 pp.31-36 |
DC, CPSY |
2015-04-17 13:00 |
Tokyo |
|
CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-7 DC2015-7 |
Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connect... [more] |
CPSY2015-7 DC2015-7 pp.37-41 |
DC, CPSY |
2015-04-17 13:25 |
Tokyo |
|
A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] |
CPSY2015-8 DC2015-8 pp.43-48 |
DC, CPSY |
2015-04-17 13:50 |
Tokyo |
|
Near Memory Processing Architecture for High Performance Atypical Applications Tadahiro Edamoto, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-9 DC2015-9 |
[more] |
CPSY2015-9 DC2015-9 pp.49-52 |
DC, CPSY |
2015-04-17 14:15 |
Tokyo |
|
Parallel Processor Architecture based on Small World Connection Hideki Mori (Meiji Univ.), Minoru Uehara, Katsuyoshi Matsumoto (Toyo Univ.) CPSY2015-10 DC2015-10 |
The technology of circuit refinement has achieved a tremendous large-scale integration, so huge VLSI systems have emerge... [more] |
CPSY2015-10 DC2015-10 pp.53-58 |
DC, CPSY |
2015-04-17 14:50 |
Tokyo |
|
[Special Invited Talk]
On Hardware for high-speed pattern matching Tsutomu Sasao (Meiji Univ.) CPSY2015-11 DC2015-11 |
High-speed pattern matching is implemented with conventional memories.
Using the concept of index generation function, ... [more] |
CPSY2015-11 DC2015-11 pp.59-66 |
DC, CPSY |
2015-04-17 15:50 |
Tokyo |
|
A parallel-operation-oriented FPGA architecture Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) CPSY2015-12 DC2015-12 |
[more] |
CPSY2015-12 DC2015-12 pp.67-70 |
DC, CPSY |
2015-04-17 16:15 |
Tokyo |
|
A Case Study on Prototyping Cloud based IoT devices Minoru Uehara (Toyo Univ.) CPSY2015-13 DC2015-13 |
[more] |
CPSY2015-13 DC2015-13 pp.71-76 |
DC, CPSY |
2015-04-17 16:40 |
Tokyo |
|
Frequency Domain aware Power Analysis based on Two Steps Hierarchal Alignment Method Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) CPSY2015-14 DC2015-14 |
The thread of side-channel attacks is pointed out in recently times. Side-channel attacks utilize power consumption or e... [more] |
CPSY2015-14 DC2015-14 pp.77-82 |
DC, CPSY |
2015-04-17 17:05 |
Tokyo |
|
Prototyping of GPS-based Item Finder System Soichiro Kanagawa, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-15 DC2015-15 |
In recent years, small high-performance equipment accumulating a large amount of information has been penetrated as poss... [more] |
CPSY2015-15 DC2015-15 pp.83-88 |