Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 09:30 |
Kanagawa |
|
A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase (SANYO Electric), Shinji Kimura (Waseda Univ.) |
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is introduced. We propose the A... [more] |
VLD2004-97 CPSY2004-63 pp.1-6 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 10:00 |
Kanagawa |
|
Reconfigurable 1-bit processor array with reduced wiring area Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a... [more] |
VLD2004-98 CPSY2004-64 pp.7-12 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 10:30 |
Kanagawa |
|
A variable clock mechanism for Dynamically Reconfigurable Processors Hideharu Amano, Yoshinori Adachi, Satoshi Tsutsumi, Kenichiro Ishikawa (Keio Univ.) |
[more] |
VLD2004-99 CPSY2004-65 pp.13-16 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 11:00 |
Kanagawa |
|
An asynchronous multi-context device with new context switching method Yoshinori Adachi, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) |
[more] |
VLD2004-100 CPSY2004-66 pp.17-22 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 11:30 |
Kanagawa |
|
A Discussion on Fault Tolerance of Dynamic Reconfigurable Device Naoki Ochi, Kentaro Nakahara, Futoshi Morie, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Reconfigurable logic devices are expected to be key devices for systems in severe environment such as spacecrafts, satel... [more] |
VLD2004-101 CPSY2004-67 pp.23-28 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 13:00 |
Kanagawa |
|
[Invited Talk]
Basics and Goals of Assertion-Based Verification Kiyoharu Hamaguchi (Osaka Univ.) |
[more] |
VLD2004-102 CPSY2004-68 pp.29-34 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 13:30 |
Kanagawa |
|
[Invited Talk]
* Masanori Imai (STARC) |
Growing complexity of SoC’s and reducing life cycle time of electronic products both are demanding higher design product... [more] |
VLD2004-103 CPSY2004-69 pp.35-38 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 14:10 |
Kanagawa |
|
A dividing technique of assertions for an interface protocol used in a divide and conquer approach of formal verification Hironao Matsushima, Akira Kitajima (OECU) |
[more] |
VLD2004-104 CPSY2004-70 pp.39-44 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 14:40 |
Kanagawa |
|
Crosstalk Driven Placement Procedure Masakazu Ochiai, Masaya Yoshikawa, Takeshi Fujino, Hidekazu Terai (Ritsumeikan University) |
This paper presents a crosstalk reduction method. At the stage of the placement processing, we considered that the effec... [more] |
VLD2004-105 CPSY2004-71 pp.45-50 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 15:20 |
Kanagawa |
|
An Instance-Specific Hardware Algorithm Using FPGAs for the Mimimum Vertex Cover Problem of a Graph Kenji Kikuchi, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
This report presents a hardware algorithm for finding a minimum vertex cover of a given graph, and shows experimental ev... [more] |
VLD2004-106 CPSY2004-72 pp.51-56 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 15:50 |
Kanagawa |
|
Solving SAT problem by PCMGTP on FPGA Shohei Kinoshita, Junichi Matsuda, Hiroshi Fujita, Miyuki Koshimura, Ryuzo Hasegawa (Kyushu Univ) |
In this paper, a new design of the SAT solver PCMGTP implemented on an FPGA chip is described. Although the previous imp... [more] |
VLD2004-107 CPSY2004-73 pp.57-62 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 16:20 |
Kanagawa |
|
Design of cellular simulation platform for SBML model Yow Iwaoka, Yasunori Osana, Tomonori Fukushima, Masato Yoshimi (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
Computer simulation in widely used in biochemistry research.
However, simulating large-scale model requires a large com... [more] |
VLD2004-108 CPSY2004-74 pp.63-68 |
CPSY, VLD, IPSJ-SLDM |
2005-01-25 16:50 |
Kanagawa |
|
Architecture for Crossover based on Sequence Pair Ryousuke Kanemitsu, Akinori Bito, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan University) |
The floor planning technique that uses GA based on the sequence pair for the solution search is proposed and it obtains ... [more] |
VLD2004-109 CPSY2004-75 pp.69-74 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 09:30 |
Kanagawa |
|
Preliminary Implementation of Volume Rendering Circuit onto an FPGA-based Visualization Accelerator Dai Okamura, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita (Kyoto Univ.) |
This paper introduces an FPGA-based PCIcard for Parallel Visualization of Large Volume Data.In order to implement memory... [more] |
VLD2004-110 CPSY2004-76 pp.1-6 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 10:00 |
Kanagawa |
|
Hardware Realization of Panoramic Image Generation Function Yukinori Nagase, Takao Kawamura, Kazunori Sugahara (Tottori Univ.) |
In this paper, a video camera for TV conferences are proposed.
Proposed camera has panoramic image generation functions... [more] |
VLD2004-111 CPSY2004-77 pp.7-11 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 10:30 |
Kanagawa |
|
Hardware Realization of Active Contour Model and Its Application for Word Recognition by Lip Reading Yusuke Sasaki, Takao Kawamura, Kazunori Sugahara (Tottori Univ.) |
(To be available after the conference date) [more] |
VLD2004-112 CPSY2004-78 pp.13-17 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 11:00 |
Kanagawa |
|
FPGA-based Sound Analysis System for the Marine Organism Yuki Shimizu (Waseda Univ.), Rajendar Bahl (IIT), Masao Sakata, Tamaki Ura (Tokyo Univ.), Masao Yanagisawa (Waseda Univ.) |
Many parts of sea environment are unclear, so a lot of research activities are trying to explore and analyze it with tec... [more] |
VLD2004-113 CPSY2004-79 pp.19-24 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 11:30 |
Kanagawa |
|
Detection of the audio watermark on FPGA Kazuhiro Sakakibara, Yasushi Inoguchi (JAIST) |
(To be available after the conference date) [more] |
VLD2004-114 CPSY2004-80 pp.25-30 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 13:00 |
Kanagawa |
|
[Invited Talk]
* Takashi Miyamori (TOSHIBA) |
MeP(Media embedded Processor) which is integrated into SoCs of digital consumer products and digital communication produ... [more] |
VLD2004-115 CPSY2004-81 pp.31-36 |
CPSY, VLD, IPSJ-SLDM |
2005-01-26 13:40 |
Kanagawa |
|
Design and Development of Microprocessors on a Hardware/Software Colearning System Koichiro Nakamura, Hoang Anh Tuan, Shigeru Oyanagi, Katsuhiro Yamazaki (Ritsumeikan University) |
The hardware/software co-learning system helps user to learn both hardware and software such as assembly programming, pr... [more] |
VLD2004-116 CPSY2004-82 pp.37-42 |