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Technical Committee on Computer Systems (CPSY)  (Searched in: 2012)

Search Results: Keywords 'from:2013-01-16 to:2013-01-16'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 29  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
09:10		 Kanagawa   Architecture Evaluation of a Reconfigurable Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) VLD2012-107 CPSY2012-56 RECONF2012-61		 In this paper, we discuss the detailed structure of MPLD, an architecture for
realizing reconfigurable devices. MPLD co... [more]		 VLD2012-107 CPSY2012-56 RECONF2012-61
pp.1-6
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
09:35		 Kanagawa   A Design Method of Network-on-Chip Architecture for FPGA
Hideki Katabami, Hiroshi Saito (Aizu Univ.) VLD2012-108 CPSY2012-57 RECONF2012-62		 This paper proposes a design method for a Globally-Asynchronous Locally-Synchronous Network-on-Chip (GALS-NoC) on Altera... [more] VLD2012-108 CPSY2012-57 RECONF2012-62
pp.7-12
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
10:00		 Kanagawa   A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer
Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63		 3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] VLD2012-109 CPSY2012-58 RECONF2012-63
pp.13-18
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
10:35		 Kanagawa   Performance Evaluation of Parametalized Data Compression Hardware for Floating-Point Data Stream
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) VLD2012-110 CPSY2012-59 RECONF2012-64		  [more] VLD2012-110 CPSY2012-59 RECONF2012-64
pp.19-24
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
11:00		 Kanagawa   An Architecture for IPv6 Lookup Using Parallel Index Generation Units
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2012-111 CPSY2012-60 RECONF2012-65		 This paper shows an area-efficiency and high-performance
architecture for the IPv6 lookup using parallel index generat... [more]		 VLD2012-111 CPSY2012-60 RECONF2012-65
pp.25-30
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
11:25		 Kanagawa   Implementation of a neural network for FPGA-based digital DC-DC converters
Yoshihiko Yamabe, Masashi Motomura, Kentaro Yamashita, Hidenori Maruta, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.) VLD2012-112 CPSY2012-61 RECONF2012-66		 In this paper, we present implementation and evaluation of an FPGA-based neural network for controlling DC-DC converters... [more] VLD2012-112 CPSY2012-61 RECONF2012-66
pp.31-36
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
13:00		 Kanagawa   [Invited Talk] Challenges and Opportunities for Normally-Off Computing
Hiroshi Nakamura (U. Tokyo) VLD2012-113 CPSY2012-62 RECONF2012-67		  [more] VLD2012-113 CPSY2012-62 RECONF2012-67
p.37
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:10		 Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68		 Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]		 VLD2012-114 CPSY2012-63 RECONF2012-68
pp.39-44
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:35		 Kanagawa   Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69		 RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the... [more] VLD2012-115 CPSY2012-64 RECONF2012-69
pp.45-50
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
15:00		 Kanagawa   Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation
Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-116 CPSY2012-65 RECONF2012-70		  [more] VLD2012-116 CPSY2012-65 RECONF2012-70
pp.51-56
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
15:35		 Kanagawa   Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2012-117 CPSY2012-66 RECONF2012-71		 This paper presents an enhanced method of testing validity of arithmetic optimization of C compilers using random progra... [more] VLD2012-117 CPSY2012-66 RECONF2012-71
pp.57-62
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
16:00		 Kanagawa   Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor
Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72		 Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] VLD2012-118 CPSY2012-67 RECONF2012-72
pp.63-68
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
16:25		 Kanagawa   Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu
Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73		 This article presents an improvement over the hardware accelerator
tightly coupled with a CPU. While the previously pr... [more]		 VLD2012-119 CPSY2012-68 RECONF2012-73
pp.69-73
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
17:00		 Kanagawa   Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB)
Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74		 Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] VLD2012-120 CPSY2012-69 RECONF2012-74
pp.75-80
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
17:25		 Kanagawa   An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths
Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) VLD2012-121 CPSY2012-70 RECONF2012-75		 Due to the increase of operation frequency, influence of routing delays is increasing. So it is important to obtain the ... [more] VLD2012-121 CPSY2012-70 RECONF2012-75
pp.81-86
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
17:50		 Kanagawa   The Rohm0.18um Chip Design Trial Using AllianceEDA Tool-set and Cell Library Based on Lambda Rule for Deep-submicron Process -- Trial of Place and Routing Tools --
Tatsuya Hosokawa, Naohiko Shimizu (Tokai Univ.) VLD2012-122 CPSY2012-71 RECONF2012-76		 We have developed chip design flow using open source EDA tool-set and lambda rule based cell library and succeed trial m... [more] VLD2012-122 CPSY2012-71 RECONF2012-76
pp.87-92
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
09:10		 Kanagawa   An accelerator with minimal data transferring using ring connections
He Guan, Jun Yao, Yasuhiko Nakashima (NAIST) VLD2012-123 CPSY2012-72 RECONF2012-77		 (To be available after the conference date) [more] VLD2012-123 CPSY2012-72 RECONF2012-77
pp.93-98
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
09:35		 Kanagawa   Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance
Takumi Ishida, Daiki Yamazaki, Masakazu Taniguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2012-124 CPSY2012-73 RECONF2012-78		  [more] VLD2012-124 CPSY2012-73 RECONF2012-78
pp.99-104
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
10:00		 Kanagawa   FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams
Yasin Oge, Masato Yoshimi (Univ. of Electro-Comm.), Takefumi Miyoshi (e-trees), Hideyuki Kawashima (Univ. of Tsukuba), Hidetsugu Irie, Tsutomu Yoshinaga (Univ. of Electro-Comm.) VLD2012-125 CPSY2012-74 RECONF2012-79		 This paper proposes an order-agnostic implementation of sliding-window aggregate queries on an FPGA. Instead of bufferin... [more] VLD2012-125 CPSY2012-74 RECONF2012-79
pp.105-110
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
10:35		 Kanagawa   Low power packet transfer technique on distributed real-time systems
Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2012-126 CPSY2012-75 RECONF2012-80		 In this paper, we propose a low-power technique for real-time communication standard Responsive Link in which data rate ... [more] VLD2012-126 CPSY2012-75 RECONF2012-80
pp.111-116
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