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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Akira Nagoya (Okayama Univ.) Vice Chair: Tetsuo Hironaka (Hiroshima City Univ.), Shorin Kyo (NEC)
Secretary: Tomonori Izumi (Ritsumeikan Univ.), Yohei Hori (Chuo Univ.)
Assistant: Nobuya Watanabe (Okayama Univ.)

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Technical Committee on VLSI Design Technologies (VLD)
Chair: Atsushi Takahashi (Osaka Univ.) Vice Chair: Ikuo Harada (NTT)
Secretary: Nozomu Togawa (Waseda Univ.), Akihisa Yamada (Sharp)

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Technical Committee on Computer Systems (CPSY)
Chair: Shuichi Sakai (Univ. of Tokyo) Vice Chair: Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.)
Secretary: Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC)
Assistant: Hidetsugu Irie (Univ. of Tokyo)

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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Shinji Kimura
Secretary: Takashi Aoki, Naoyuki Hoshi, Kenshu Seto

DATE:
Tue, Jan 26, 2010 09:00 - 17:35
Wed, Jan 27, 2010 09:00 - 16:45

PLACE:
Hiyoshi Campus, Keio University(1-minute walk from Hiyoshi Station (Tokyu-Toyoko Line))

TOPICS:
FPGA Applications, etc

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Tue, Jan 26 AM Development Environment (09:00 - 10:40)
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(1)/RECONF 09:00 - 09:25
A study of software development environment for dynamic-reconfigurable processor MuCCRA-3.
Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.)

(2)/RECONF 09:25 - 09:50
Reducing scheduling overheads in Dynamically Reconfigurable Processors
Ratna Krishnamoorthy (Univ of Tokyo), Keshavan Varadarajan, Mythri Alle (IISc), Ranjani Narayan (Morphing Machines), Masahiro Fujita (Univ of Tokyo), S K Nandy (IISc)

(3)/VLD 09:50 - 10:15
Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.)

(4)/RECONF 10:15 - 10:40
Evaluation using Applications for RC-OS which supports Reconfigurable Computer System
Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ)

----- Break ( 10 min. ) -----

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Tue, Jan 26 AM Network (10:50 - 11:40)
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(5)/RECONF 10:50 - 11:15
A network deliverable hw/sw complex, video codec
Ryosuke Kurogi, Kentaro Hanai, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo Univ. of Agr and Tech.)

(6)/RECONF 11:15 - 11:40
Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA
Jaeseong Kim, Shingo Yoshizawa, Yusaku Kaneta, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)

----- Lunch Break ( 85 min. ) -----

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Tue, Jan 26 PM Application 1 (13:05 - 14:20)
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(7)/RECONF 13:05 - 13:30
FPGA Implementation of Discrete Wavlet Transform Using Impulse C
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.)

(8)/RECONF 13:30 - 13:55
An FPGA Implementation of Array Processor Performing 3D-DCT Effectively
Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu)

(9)/RECONF 13:55 - 14:20
Computer Aided Detection System Implementation for recognize cancer in Mammograms over a FPGA
Yessica Suarez Henandez (IPN/Univ. of Electro-Comm.), Sayaka Akioka, Tsutomu Yoshinaga, Volodymyr Ponomaryov, Gonzalo Duchen Sanchez (Univ. of Electro-Comm.)

----- Break ( 10 min. ) -----

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Tue, Jan 26 PM Bus and Interconnect Architecture (14:30 - 15:45)
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(10)/CPSY 14:30 - 14:55
A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure
Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.)

(11)/RECONF 14:55 - 15:20
Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(12) 15:20 - 15:45


----- Break ( 10 min. ) -----

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Tue, Jan 26 PM Datapath Optimization (15:55 - 17:35)
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(13)/VLD 15:55 - 16:20
Residue-Binary Conversion Using Signed-Digit Number Arithmetic
Changjun Jiang, Shugang Wei (Gunma Univ.)

(14)/VLD 16:20 - 16:45
Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation
Mingda Zhang, Shugang Wei (Gunma Univ.)

(15)/RECONF 16:45 - 17:10
Hardware Specialization of Digital Filters for Vibration Control
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.)

(16)/VLD 17:10 - 17:35
A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

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Wed, Jan 27 AM Low-power Design (09:00 - 09:50)
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(17)/RECONF 09:00 - 09:25
Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)

(18)/RECONF 09:25 - 09:50
Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array
Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)

----- Break ( 10 min. ) -----

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Wed, Jan 27 AM Acceleration Techniques (10:00 - 11:40)
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(19)/CPSY 10:00 - 10:25
Granularity Optimization Method for AES Encryption Implementation on CUDA
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)

(20)/RECONF 10:25 - 10:50
Effective Hardware Task Context Switching in Virtex-4 FPGAs
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.)

(21)/RECONF 10:50 - 11:15
Hardware Acceleration in a Scalable FPGA System
Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)

(22)/RECONF 11:15 - 11:40
Expansion of Hardware in a Scalable FPGA System
Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)

----- Lunch Break ( 60 min. ) -----

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Wed, Jan 27 PM Application 2 (12:40 - 13:55)
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(23)/RECONF 12:40 - 13:05
An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution
Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)

(24)/RECONF 13:05 - 13:30
Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ)

(25)/RECONF 13:30 - 13:55
A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.)

----- Break ( 10 min. ) -----

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Wed, Jan 27 PM Dependable Design (14:05 - 15:20)
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(26)/RECONF 14:05 - 14:30
An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs
Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)

(27)/RECONF 14:30 - 14:55
Fault Recovery Technique for Softcore Processor using Partial Reconfiguration
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(28)/VLD 14:55 - 15:20
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)

----- Break ( 10 min. ) -----

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Wed, Jan 27 PM Optically Reconfigurable Architecture (15:30 - 16:45)
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(29)/RECONF 15:30 - 15:55
A remote dynamic optically reconfigurable gate array using a fiber array
Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.)

(30)/RECONF 15:55 - 16:20
Compensation method for photodiode characteristics variation using an analog configuration context
Yuji Aoyama, Minoru Watanabe (Shizuoka Univ.)

(31)/RECONF 16:20 - 16:45
A programmable optically reconfigurable gate array with a silver-halide holographic memory
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on Reconfigurable Systems (RECONF) ===

# SECRETARY:


=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Wed, Mar 10, 2010 - Fri, Mar 12, 2010: [Wed, Jan 20], Topics: Design Technology for System-on-Silicon

# SECRETARY:
Nozomu Togawa (Waseda Univ.)
E-mail: ntogawa@waseda.jp
Tel: +81-3-5286-3908, Fax: +81-3-3208-7439

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Technical Committee on Computer Systems (CPSY) ===
# FUTURE SCHEDULE:

Fri, Mar 26, 2010 - Sun, Mar 28, 2010: [Fri, Jan 22]
Tue, Apr 13, 2010: [Wed, Feb 17]

# SECRETARY:


=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:

Fri, Mar 26, 2010 - Sun, Mar 28, 2010: [Fri, Jan 22]

# SECRETARY:



Last modified: 2010-01-06 20:00:10


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