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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Atsushi Takahashi (Osaka Univ.)
Vice Chair Ikuo Harada (NTT)
Secretary Nozomu Togawa (Waseda Univ.), Akihisa Yamada (Sharp)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Shuichi Sakai (Univ. of Tokyo)
Vice Chair Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.)
Secretary Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC)
Assistant Hidetsugu Irie (Univ. of Tokyo)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Akira Nagoya (Okayama Univ.)
Vice Chair Tetsuo Hironaka (Hiroshima City Univ.), Shorin Kyo (NEC)
Secretary Tomonori Izumi (Ritsumeikan Univ.), Yohei Hori (Chuo Univ.)
Assistant Nobuya Watanabe (Okayama Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Shinji Kimura
Secretary Takashi Aoki, Naoyuki Hoshi, Kenshu Seto

Conference Date Tue, Jan 26, 2010 09:00 - 17:35
Wed, Jan 27, 2010 09:00 - 16:45
Topics FPGA Applications, etc 
Conference Place Hiyoshi Campus, Keio University 
Transportation Guide 1-minute walk from Hiyoshi Station (Tokyu-Toyoko Line)
Copyright
and
reproduction
以下の論文すべての著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Tue, Jan 26 AM  Development Environment
09:00 - 10:40
(1)
RECONF
09:00-09:25 A study of software development environment for dynamic-reconfigurable processor MuCCRA-3. VLD2009-69 CPSY2009-51 RECONF2009-54 Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.)
(2)
RECONF
09:25-09:50 Reducing scheduling overheads in Dynamically Reconfigurable Processors VLD2009-70 CPSY2009-52 RECONF2009-55 Ratna Krishnamoorthy (Univ of Tokyo), Keshavan Varadarajan, Mythri Alle (IISc), Ranjani Narayan (Morphing Machines), Masahiro Fujita (Univ of Tokyo), S K Nandy (IISc)
(3)
VLD
09:50-10:15 Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization VLD2009-71 CPSY2009-53 RECONF2009-56 Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.)
(4)
RECONF
10:15-10:40 Evaluation using Applications for RC-OS which supports Reconfigurable Computer System VLD2009-72 CPSY2009-54 RECONF2009-57 Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ)
  10:40-10:50 Break ( 10 min. )
Tue, Jan 26 AM  Network
10:50 - 11:40
(5)
RECONF
10:50-11:15 A network deliverable hw/sw complex, video codec VLD2009-73 CPSY2009-55 RECONF2009-58 Ryosuke Kurogi, Kentaro Hanai, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo Univ. of Agr and Tech.)
(6)
RECONF
11:15-11:40 Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA VLD2009-74 CPSY2009-56 RECONF2009-59 Jaeseong Kim, Shingo Yoshizawa, Yusaku Kaneta, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)
  11:40-13:05 Lunch Break ( 85 min. )
Tue, Jan 26 PM  Application 1
13:05 - 14:20
(7)
RECONF
13:05-13:30 FPGA Implementation of Discrete Wavlet Transform Using Impulse C VLD2009-75 CPSY2009-57 RECONF2009-60 Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.)
(8)
RECONF
13:30-13:55 An FPGA Implementation of Array Processor Performing 3D-DCT Effectively VLD2009-76 CPSY2009-58 RECONF2009-61 Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu)
(9)
RECONF
13:55-14:20 Computer Aided Detection System Implementation for recognize cancer in Mammograms over a FPGA VLD2009-77 CPSY2009-59 RECONF2009-62 Yessica Suarez Henandez (IPN/Univ. of Electro-Comm.), Sayaka Akioka, Tsutomu Yoshinaga, Volodymyr Ponomaryov, Gonzalo Duchen Sanchez (Univ. of Electro-Comm.)
  14:20-14:30 Break ( 10 min. )
Tue, Jan 26 PM  Bus and Interconnect Architecture
14:30 - 15:45
(10)
CPSY
14:30-14:55 A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure VLD2009-78 CPSY2009-60 RECONF2009-63 Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.)
(11)
RECONF
14:55-15:20 Design of Reconfigurable Logic Device based on Variable Grain Logic Cell VLD2009-79 CPSY2009-61 RECONF2009-64 Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(12) 15:20-15:45  
  15:45-15:55 Break ( 10 min. )
Tue, Jan 26 PM  Datapath Optimization
15:55 - 17:35
(13)
VLD
15:55-16:20 Residue-Binary Conversion Using Signed-Digit Number Arithmetic VLD2009-80 CPSY2009-62 RECONF2009-65 Changjun Jiang, Shugang Wei (Gunma Univ.)
(14)
VLD
16:20-16:45 Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation VLD2009-81 CPSY2009-63 RECONF2009-66 Mingda Zhang, Shugang Wei (Gunma Univ.)
(15)
RECONF
16:45-17:10 Hardware Specialization of Digital Filters for Vibration Control VLD2009-82 CPSY2009-64 RECONF2009-67 Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.)
(16)
VLD
17:10-17:35 A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching VLD2009-83 CPSY2009-65 RECONF2009-68 Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
Wed, Jan 27 AM  Low-power Design
09:00 - 09:50
(17)
RECONF
09:00-09:25 Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control VLD2009-84 CPSY2009-66 RECONF2009-69 Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
(18)
RECONF
09:25-09:50 Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array VLD2009-85 CPSY2009-67 RECONF2009-70 Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)
  09:50-10:00 Break ( 10 min. )
Wed, Jan 27 AM  Acceleration Techniques
10:00 - 11:40
(19)
CPSY
10:00-10:25 Granularity Optimization Method for AES Encryption Implementation on CUDA VLD2009-86 CPSY2009-68 RECONF2009-71 Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)
(20)
RECONF
10:25-10:50 Effective Hardware Task Context Switching in Virtex-4 FPGAs VLD2009-87 CPSY2009-69 RECONF2009-72 Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.)
(21)
RECONF
10:50-11:15 Hardware Acceleration in a Scalable FPGA System VLD2009-88 CPSY2009-70 RECONF2009-73 Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)
(22)
RECONF
11:15-11:40 Expansion of Hardware in a Scalable FPGA System VLD2009-89 CPSY2009-71 RECONF2009-74 Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)
  11:40-12:40 Lunch Break ( 60 min. )
Wed, Jan 27 PM  Application 2
12:40 - 13:55
(23)
RECONF
12:40-13:05 An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution VLD2009-90 CPSY2009-72 RECONF2009-75 Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)
(24)
RECONF
13:05-13:30 Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers VLD2009-91 CPSY2009-73 RECONF2009-76 Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ)
(25)
RECONF
13:30-13:55 A Packet Classifier Using a Parallel Branching Program Machine VLD2009-92 CPSY2009-74 RECONF2009-77 Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.)
  13:55-14:05 Break ( 10 min. )
Wed, Jan 27 PM  Dependable Design
14:05 - 15:20
(26)
RECONF
14:05-14:30 An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs VLD2009-93 CPSY2009-75 RECONF2009-78 Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(27)
RECONF
14:30-14:55 Fault Recovery Technique for Softcore Processor using Partial Reconfiguration VLD2009-94 CPSY2009-76 RECONF2009-79 Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(28)
VLD
14:55-15:20 An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level VLD2009-95 CPSY2009-77 RECONF2009-80 Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)
  15:20-15:30 Break ( 10 min. )
Wed, Jan 27 PM  Optically Reconfigurable Architecture
15:30 - 16:45
(29)
RECONF
15:30-15:55 A remote dynamic optically reconfigurable gate array using a fiber array VLD2009-96 CPSY2009-78 RECONF2009-81 Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.)
(30)
RECONF
15:55-16:20 Compensation method for photodiode characteristics variation using an analog configuration context VLD2009-97 CPSY2009-79 RECONF2009-82 Yuji Aoyama, Minoru Watanabe (Shizuoka Univ.)
(31)
RECONF
16:20-16:45 A programmable optically reconfigurable gate array with a silver-halide holographic memory VLD2009-98 CPSY2009-80 RECONF2009-83 Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Nozomu Togawa (Waseda Univ.)
E-: n
Tel: +81-3-5286-3908, Fax: +81-3-3208-7439 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address  
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  


Last modified: 2010-01-06 20:00:10


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