|
|
| Chair |
|
Toshinori Sueyoshi |
| Vice Chair |
|
Akira Nagoya, Tomomi Sato |
| Secretary |
|
Tetsuo Hironaka, Yuichiro Shibata |
| Assistant |
|
Masahiro Iida |
|
Thu, May 12 AM
09:30 - 12:00 |
| (1) |
09:30-10:00 |
A Reconfigurable Embedded Decompressor for LSI Testing |
Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (2) |
10:00-10:30 |
Development of clustering tool to reduce area of chip and delay |
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (3) |
10:30-11:00 |
Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure |
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| (4) |
11:00-11:30 |
Implementation of an SMT Processor and its Reconfigurable Cache with FPGA |
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo (Tokyo University of Agriculture and Technology) |
| (5) |
11:30-12:00 |
Improvement of Signature-based Phase Detection and its Application to Power Reduction in Caches |
Yuya Ueno, Luong D. Hung (Tokyo Univ.), Masanori Takada, Daisuke Tashiro (Hitachi), Shuichi Sakai (Tokyo Univ.) |
Thu, May 12 PM
13:00 - 14:00 |
| (6) |
13:00-14:00 |
[Invited Talk]
A general view on VLSI design methodology |
Yukihiro Nakamura (Kyoto Univ.) |
Thu, May 12 PM
14:00 - 15:30 |
| (7) |
14:00-14:30 |
Design of a Heap-tree Based Scalable Stochastic Biochemical Simulator on an FPGA |
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
| (8) |
14:30-15:00 |
Scheduling of Rate Law Functions for an FPGA-based Biochemical Simulator |
Naoki Iwanaga, Yuichiro Shibata (Nagasaki Univ.), Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano (Keio Univ), Akira Funahashi, Noriko Hiroi, Hiroaki Kitano (JST), Kiyoshi Oguri (Nagasaki Univ.) |
| (9) |
15:00-15:30 |
Implementation and Evaluation of Numerical Integrators on ReCSiP |
Yasunori Osana, Masato Yoshimi, Yow Iwaoka (Keio Univ.), Akira Funahashi, Noriko Hiroi (ERATO-SORST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (ERATO-SORST), Hideharu Amano (Keio Univ.) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Thu, May 12 PM
15:45 - 18:15 |
| (10) |
15:45-16:15 |
Analyses of Operating Speed and Power Consumption in Flex Power FPGA
-- From Circuit Level To Chip Level -- |
Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| (11) |
16:15-16:45 |
Area Overhead Estimation for Vth Control in Flex Power FPGA |
Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| (12) |
16:45-17:15 |
Reducing the Delay by Using the Small-World Network Structure |
Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (13) |
17:15-17:45 |
Code Scheduling in Consideration of Place and Wire in Back End Compiler for PARS |
Ryuji Hada, Takeshi Takeuchi, Takeshi Fukuda, Kazuya Tanigawa, Tetsuo Hironaka (HCU) |
| (14) |
17:45-18:15 |
A Simulation Platform for Evaluating Granularity of Self-Reconfigurable Device |
Shin'ichi Kouyama, Futoshi Morie, Kentaro Nakahara (Kyoto Univ.), Tomonori Izumi (Ritsumeikan Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Fri, May 13 AM
09:00 - 12:00 |
| (15) |
09:00-09:30 |
Development of a testbed RCPII to evaluate effects of a real environment for a reconfigurable computing |
Kosei Shimoo, Akira Yamawaki, Masahiko Iwane (KIT) |
| (16) |
09:30-10:00 |
An implementation of number-plate recognition algorithm on reconfigurable system |
Takamasa Kanamori, Shizuto Fukuda (Keio Univ.), Yoshiaki Ajioka (Ecchandes), Masatoshi Arai (CalsonicKansei), Shinya Hashimoto (MEITEC), Hideharu Amano (Keio Univ.) |
| (17) |
10:00-10:30 |
Experiment on number recognition for parallel operation |
Masatoshi Arai (CalsonicKansei), Shinya Hashimoto (MEITEC), Yoshiaki Ajioka (Ecchandes), Takamasa Kanamori, Shizuto Fukuda, Hideharu Amano (Keio Univ.) |
| (18) |
10:30-11:00 |
Reconfigurable 3D-FFT processor |
Tohru Sasaki (APM), Umpei Nagashima (AIST) |
| (19) |
11:00-11:30 |
Data-Supplying Subsystem for the Parallel Reconfigurable Image Processing System |
Akiyoshi Wakatani (Konan Univ.), Hiroshi Kadota (Kyushu Univ.) |
| (20) |
11:30-12:00 |
Developing a parallel reconfigurable system for physics computations |
Tsuyoshi Hamada, Naohito Nakasato (RIKEN) |
Fri, May 13 PM
13:00 - 14:00 |
| (21) |
13:00-14:00 |
[Invited Talk]
Programmable Device Technologies for SoC Embedded Applications |
Masami Nakajima, Hideyuki Noda, Kazutami Arimoto (Renesas) |
Fri, May 13 PM
14:00 - 15:30 |
| (22) |
14:00-14:30 |
A performance evaluation of SIMD type accelerator for JPEG2000 application |
Fumiaki Senoue, Kozo Komoda, Masahiro Iida, Morihiro Kuga (Kumamoto Univ.), Hideyuki Noda, Masami Nakajima (Renesas), Toshinori Sueyoshi (Kumamoto Univ.) |
| (23) |
14:30-15:00 |
A high-speed real number computation using simple SIMD operations |
Hiroyuki Yamasaki, Masahiro Iida (Kumamoto Univ.), Katsuya Mizumoto, Osamu Yamamoto (Renesas), Toshinori Sueyoshi (Kumamoto Univ.) |
| (24) |
15:00-15:30 |
A Proposal of Template Reconfiguration Method |
Masayasu Suzuki, Hideharu Amano (Keio Univ.) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Fri, May 13 PM
15:45 - 18:15 |
| (25) |
15:45-16:15 |
An Analysis of Fixed Point Arithmetic for DRP |
Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| (26) |
16:15-16:45 |
Implementation of Active Direction-Pass Filter on Dynamically Reconfigurable Processor |
Shunsuke Kurotaki, Noriaki Suzuki (Keio Univ.), Kazuhiro Nakadai (HRI), Hiroshi G. Okuno (Kyoto Univ.), Hideharu Amano (Keio Univ.) |
| (27) |
16:45-17:15 |
Implementation of Simplified Back Propagation Algorithm on a Dynamically Reconfigurable Device PCA-2 |
Tomoko Ootsuka, Keigo Kurata, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aizu) |
| (28) |
17:15-17:45 |
Robot Vision System with Three Dimensionally Integrated Reconfigurable Image Processor |
Takeaki Sugimura, Jun Deguchi, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Atsushi Konno, Hiroyuki Kurino, Masaru Uchiyama, Mitsumasa Koyanagi (Tohoku Univ.) |
| (29) |
17:45-18:15 |
Reconfigurable sensor network based on mutual communications with reliability index |
Takeshi Fujiwara, Kensuke Komatsu, Hiroyuki Takahashi, Masaharu Nakazawa (Tokyo Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 25 minutes for presentation and 5 minutes for discussion. |
| Special Invited Talk | Each speech will have 50 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Masahiro IIDA (Kumamoto Univ.)
E- : ii        -u
TEL: +81-96-342-3649 FAX: +81-96-342-3649 |
Last modified: 2005-03-25 23:30:49
|
Notification: Mail addresses are partially hidden against SPAM.
|