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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Takashi Takenana (NEC)
Vice Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary Daisuke Fukuda (Fujitsu Labs.), Shinobu Nagayama (Hiroshima City Univ.)
Assistant Parizy Matthieu (Fujitsu Labs.)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Yasuhiko Nakashima (NAIST)
Vice Chair Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Tokyo)
Secretary Takashi Miyoshi (Fujitsu Labs.), Michihiro Koibuchi (NII)
Assistant Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Minoru Watanabe (Shizuoka Univ.)
Vice Chair Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.)
Secretary Yoshiki Yamaguchi (Univ. of Tsukuba), Kazuya Tanigawa (Hiroshima City Univ.)
Assistant Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Masahiro Fukui (Ritsumeikan Univ.)
Secretary Masao Yokoyama (Sharp), Yasuhiro Takashima (Kitakyushu City Univ.), Takeo Nishide (Toshiba)

{INFOMESITEM}
Conference Date Mon, Jan 23, 2017 13:00 - 17:40
Tue, Jan 24, 2017 09:00 - 18:10
Wed, Jan 25, 2017 09:00 - 15:15
Topics FPGA Applications, etc 
Conference Place  
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Mon, Jan 23 PM 
13:00 - 14:15
(1)
RECONF
13:00-13:25 A Hardware Acceleration of Template Matching using FPGA and MPU VLD2016-70 CPSY2016-106 RECONF2016-51 Yuji Matumoto, Youichi Tomioka, Junji Kitamichi (The University of Aizu)
(2)
RECONF
13:25-13:50 Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor VLD2016-71 CPSY2016-107 RECONF2016-52 Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.)
(3)
RECONF
13:50-14:15 GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application VLD2016-72 CPSY2016-108 RECONF2016-53 Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Keigo Nitadori (RIKEN/AICS)
  14:15-14:30 Break ( 15 min. )
Mon, Jan 23 PM 
14:30 - 16:10
(4)
RECONF
14:30-14:55 VLD2016-73 CPSY2016-109 RECONF2016-54
(5)
RECONF
14:55-15:20 VLD2016-74 CPSY2016-110 RECONF2016-55
(6)
RECONF
15:20-15:45 Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection VLD2016-75 CPSY2016-111 RECONF2016-56 Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
(7)
CPSY
15:45-16:10 Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes VLD2016-76 CPSY2016-112 RECONF2016-57 Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC)
  16:10-16:25 Break ( 15 min. )
Mon, Jan 23 PM 
16:25 - 17:40
(8)
CPSY
16:25-16:50 A Case for FPGA Based 10GbE Switch Aggregating Computation Results of GPUs VLD2016-77 CPSY2016-113 RECONF2016-58 Kazuma Takemoto, Ami Hayashi, Shin Morishima, Hiroki Matsutani (Keio Univ.)
(9)
CPSY
16:50-17:15 VLD2016-78 CPSY2016-114 RECONF2016-59
(10)
RECONF
17:15-17:40 VLD2016-90 CPSY2016-126 RECONF2016-71 Kazusa Musha (Keio Univ.), Tomohiro Kudoh (Tokyo Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
  18:00-20:00 Social ( 120 min. )
Tue, Jan 24 AM 
09:00 - 10:40
(11)
RECONF
09:00-09:25 Overview of an HLS Framework Surpporting IoT/CPS Development VLD2016-80 CPSY2016-116 RECONF2016-61 Daichi Teruya, Hironori Nakajo (TUAT)
(12)
RECONF
09:25-09:50 Framework for a Hybrid System with a pair of MCU and FPGA VLD2016-81 CPSY2016-117 RECONF2016-62 Ryota Suzuki, Nakajo Hironori (TUAT)
(13) 09:50-10:15  
(14) 10:15-10:40  
  10:40-10:55 Break ( 15 min. )
Tue, Jan 24 PM 
10:55 - 12:10
(15)
CPSY
10:55-11:20 A Case for Remote GPU Assignment for VR Applications VLD2016-82 CPSY2016-118 RECONF2016-63 Shin Morishima, Masahiro Okazaki (Keio Univ.), Hiroki Matsutani (Keio Univ.PRESTO/NII)
(16)
CPSY
11:20-11:45 Evaluation of the PEACH3 used for communication in application VLD2016-83 CPSY2016-119 RECONF2016-64 Takahiro Kaneda (Keio Univ.), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ.)
(17)
CPSY
11:45-12:10 Optimization of Fresnel hologram computation on GPU using decomposition method VLD2016-84 CPSY2016-120 RECONF2016-65 Shinpei Watanabe (Utsunomiya Univ.), Boaz Jessie Jackin (NICT), Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba (Utsunomiya Univ.)
  12:10-13:30 Lunch ( 80 min. )
Tue, Jan 24 PM 
13:30 - 15:10
(18)
CPSY
13:30-13:55 Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops VLD2016-85 CPSY2016-121 RECONF2016-66 Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.)
(19)
CPSY
13:55-14:20 Expression of Positional registers for Tamper resistance VLD2016-86 CPSY2016-122 RECONF2016-67 Kiyohiro Sato, Naoki Fujieda, Shuichi Ichikawa (TUT)
(20)
RECONF
14:20-14:45 Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption VLD2016-87 CPSY2016-123 RECONF2016-68 Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.)
(21) 14:45-15:10  
  15:10-15:25 Break ( 15 min. )
Tue, Jan 24 PM 
15:25 - 16:40
(22)
RECONF
15:25-15:50 Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement VLD2016-88 CPSY2016-124 RECONF2016-69 Haruyoshi Yonekawa, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido Univ.)
(23)
RECONF
15:50-16:15 A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization VLD2016-79 CPSY2016-115 RECONF2016-60 Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.)
(24)
RECONF
16:15-16:40 VLD2016-89 CPSY2016-125 RECONF2016-70
  16:40-16:55 Break ( 15 min. )
Tue, Jan 24 PM 
16:55 - 18:10
(25)
RECONF
16:55-17:20 FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data VLD2016-91 CPSY2016-127 RECONF2016-72 Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.)
(26)
VLD
17:20-17:45 A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption VLD2016-92 CPSY2016-128 RECONF2016-73 Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(27)
RECONF
17:45-18:10 Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs VLD2016-93 CPSY2016-129 RECONF2016-74 Thiem Van Chu, Kenji Kise (Tokyo Tech)
Wed, Jan 25 AM 
09:00 - 10:40
(28)
CPSY
09:00-09:25 VLD2016-94 CPSY2016-130 RECONF2016-75
(29)
VLD
09:25-09:50 Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit VLD2016-95 CPSY2016-131 RECONF2016-76 Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH)
(30)
VLD
09:50-10:15 Finite state machine design for high accurate stochastic computing VLD2016-96 CPSY2016-132 RECONF2016-77 Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(31)
VLD
10:15-10:40 MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data VLD2016-97 CPSY2016-133 RECONF2016-78 Junya Akaike, Kimiyoshi Usami (SIT)
  10:40-10:55 Break ( 15 min. )
Wed, Jan 25 PM 
10:55 - 12:35
(32)
VLD
10:55-11:20 Thermal transient analysis and evaluation of three-dimensional stacked chips VLD2016-98 CPSY2016-134 RECONF2016-79 Shogo Yasuda, Kimiyoshi Usami (SIT)
(33) 11:20-11:45  
(34) 11:45-12:10  
(35) 12:10-12:35  
  12:35-14:00 Lunch ( 85 min. )
Wed, Jan 25 PM 
14:00 - 15:15
(36)
CPSY
14:00-14:25 An FPGA NIC Based Distributed Ledger Caching for Blockchain VLD2016-99 CPSY2016-135 RECONF2016-80 Yuma Sakakibara, Kohei Nakamura (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII)
(37)
CPSY
14:25-14:50 Proxy Responses for MapReduce Delayed Task Using 10GbE FPGA Switch VLD2016-100 CPSY2016-136 RECONF2016-81 Koya Mitsuzuka, Ami Hayashi (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII)
(38)
CPSY
14:50-15:15 Design and Evaluation of A Suboptimal Unidirectional Network VLD2016-101 CPSY2016-137 RECONF2016-82 Tomohiro Totoki, Hiroshi Nakahara, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Daisuke Fukuda (Fujitsu Laboratories)
E-: d- 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Tomoaki TSUMURA (Nagoya Inst. of Tech.)
E-:

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/ 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Yuki KOBAYASHI
NEC Corporation
e-: y-bahqc
Tel: +81-44-431-7540
Fax: +81-44-435-1096 
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Yasuhiro Takashima (University of Kitakyushu)
E sldm2015isenvk-u 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2017-01-18 08:34:45


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