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===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Minoru Watanabe (Shizuoka Univ.)
Vice Chair: Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.)
Secretary: Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant: Kazuya Tanikagawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)

===============================================
Technical Committee on VLSI Design Technologies (VLD)
Chair: Yusuke Matsunaga (Kyushu Univ.) Vice Chair: Takashi Takenana (NEC)
Secretary: Hiroyuki Tomiyama (Ritsumeikan Univ.), Daisuke Fukuda (Fujitsu Labs.)
Assistant: Ittetsu Taniguchi (Ritsumeikan Univ.)

===============================================
Technical Committee on Component Parts and Materials (CPM)
Chair: Satoru Noge (Numazu National College of Tech.) Vice Chair: Fumihiko Hirose (Yamagata Univ.)
Secretary: Junichi Kodate (NTT), Nobuyuki Iwata (Nihon Univ.)
Assistant: Takashi Sakamoto (NTT), Yuichi Nakamura (Toyohashi Univ. of Tech.)

===============================================
Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Minoru Fujishima (Hiroshima Univ.) Vice Chair: Hideto Hidaka (Renesas)
Secretary: Takeshi Yoshida (Hiroshima Univ.)
Assistant: Makoto Takamiya (Univ. of Tokyo), Hiroe Iwasaki (NTT), Takashi Hashimoto (Panasonic), Hiroyuki Ito (Tokyo Inst. of Tech.), Pham Konkuha (Univ. of Electro-Comm.)

===============================================
Technical Committee on Computer Systems (CPSY)
Chair: Yasuhiko Nakashima (NAIST)
Vice Chair: Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Tokyo)
Secretary: Takashi Miyoshi (Fujitsu Labs.), Michihiro Koibuchi (NII)
Assistant: Shinya Takameda (NAIST), Takeshi Ohkawa (Utsunomiya Univ.)

===============================================
Technical Committee on Dependable Computing (DC)
Chair: Nobuyasu Kanekawa (Hitachi) Vice Chair: Michiko Inoue (NAIST)
Secretary: Koji Iwata (RTRI), Masayoshi Yoshimura (Kyoto Sangyo Univ.)

===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Masahiro Fukui (Ritsumeikan Univ.)
Secretary: Masao Yokoyama (Sharp), Yasuhiro Takashima (Kitakyushu City Univ.), Takeo Nishide (Toshiba)

DATE:
Tue, Dec 1, 2015 12:45 - 18:00
Wed, Dec 2, 2015 09:30 - 18:00
Thu, Dec 3, 2015 09:20 - 15:25

PLACE:
(http://www.nsbm.jp/kaikan/)

TOPICS:
Design Gaia 2015 -New Field of VLSI Design-

----------------------------------------
Tue, Dec 1 PM (12:45 - 13:35)
----------------------------------------

(1)/DC 12:45 - 13:10
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST)

(2)/VLD 13:10 - 13:35
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda (Univ. of Tokyo)

----------------------------------------
Tue, Dec 1 PM (12:45 - 13:35)
----------------------------------------

(3)/RECONF 12:45 - 13:10
Triple modular redundancy on a parallel-operation-oriented optically reconfigurable gate array
Yoshizumi Ito, Minoru Watanabe (Shizuoka Univ.)

(4)/RECONF 13:10 - 13:35
Fault tolerance of an inversion configuration method on an optically configurable gate array
Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.)

----------------------------------------
Tue, Dec 1 PM (12:45 - 13:35)
----------------------------------------

(5)/CPSY 12:45 - 13:10
Performance Evaluations of Document-Oriented Databases using Remote GPU Cluster
Shin Morishima, Hiroki Matsutani (Keio Univ.)

(6)/CPSY 13:10 - 13:35
A study of GPU acceleration of "source" part in Hall-thruster simulation
Takaaki Miyajima, Shinatora Cho, Naoyuki Fujita (JAXA)

----- Break ( 15 min. ) -----

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Tue, Dec 1 PM (13:50 - 15:30)
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(7)/ICD 13:50 - 14:40
[Invited Talk]
IC Chip Authentication and Guarantee
-- As Root Problems of Hardware Security --
Makoto Nagata (Kobe Univ.)

(8)/ICD 14:40 - 15:30
[Invited Talk]
Video Coding Hardware Technologies for Distributing 4K/8K Ultra High Definition Images
Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu (NTT)

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Tue, Dec 1 PM (13:50 - 15:30)
----------------------------------------

(9)/RECONF 13:50 - 14:15
Partial Recofniguration for Accelerator-in-switch
Hideharu Amano, Yuichi Sakurai, Chiharu Tsuruta (Keio Univ.)

(10)/RECONF 14:15 - 14:40
Dynamic Reconfigurable PLA on FPGA and DSL-based Design Methodology
Takefumi Miyoshi (wasalabo/e-trees), Hiroki Nakahara (ehime university), Satoshi Funada (e-trees)

(11) 14:40 - 15:05


(12)/CPSY 15:05 - 15:30
Development and Evaluation of Simulator for Cellular Neural Network
Tomoya Kameda (NAIST), Mutsumi Kimura (Ryukoku Univ.), Yasuhiko Nakashima (NAIST)

----------------------------------------
Tue, Dec 1 PM (13:50 - 15:30)
----------------------------------------

(13)/DC 13:50 - 14:15
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)

(14)/DC 14:15 - 14:40
A study on multiple path selection conditions in delay testing using design-for-testability circuit
Mori Ryosuke, Yotsuyanagi Hiroyuki, Hashizume Masaki (Tokushima Univ.)

(15)/DC 14:40 - 15:05
On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)

(16)/VLD 15:05 - 15:30
Fast Monte Carlo based timing yield calculation
Hiromitsu Awano, Takashi Sato (Kyoto Univ.)

----- Break ( 15 min. ) -----

----------------------------------------
Tue, Dec 1 PM (15:45 - 16:45)
----------------------------------------

(17) 15:45 - 16:45
[Fellow Memorial Lecture]
Improving System Dependability by VLSI Test Technology
Seiji Kajihara (KIT)

----- Break ( 15 min. ) -----

----------------------------------------
Tue, Dec 1 PM (17:00 - 18:00)
----------------------------------------

(18) 17:00 - 18:00
[Fellow Memorial Lecture]
Reconfigurable Chips, High-Level Synthesis, and EDA Business
Kazutoshi Wakabayashi (NEC)

----------------------------------------
Wed, Dec 2 AM (09:30 - 11:00)
----------------------------------------



----- Break ( 15 min. ) -----

----------------------------------------
Wed, Dec 2 AM (11:15 - 12:30)
----------------------------------------

(19)/VLD 11:15 - 11:40
Improved Method of Simulated Annealing for Unreachable Solution Space
Hiroyuki Nakano, Kunihiro Fujiyoshi (TUAT)

(20)/VLD 11:40 - 12:05
On applications of Monte-Carlo tree search algorithm for CAD problems
Yusuke Matsunaga (Kyushu Univ.)

(21) 12:05 - 12:30


----------------------------------------
Wed, Dec 2 AM (11:15 - 12:30)
----------------------------------------

(22)/RECONF 11:15 - 11:40
A Study of HW/SW Co-design Framework based on the Virtualization Technology
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(23)/RECONF 11:40 - 12:05
A Software-Oriented Design and Synthesis Platform for a Construction of Real-Time Systems on Programmable SoCs
Takuya Hatayama, Yusuke Tani, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)

(24)/VLD 12:05 - 12:30
A Study on DVFS for Heterogeneous Task Set
Mineo Kaneko (JAIST)

----------------------------------------
Wed, Dec 2 AM (11:15 - 12:30)
----------------------------------------

(25)/CPSY 11:15 - 11:40
A C Framework for Integrating Algorithm Description and CGRA Implementation
Yasuhiko Nakashima (NAIST)

(26)/CPSY 11:40 - 12:05
Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM
Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)

(27)/CPSY 12:05 - 12:30
A proposal of the light field image compression and decompression using HEVC
Takamasa Mitani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)

----- Break ( 75 min. ) -----

----------------------------------------
Wed, Dec 2 PM (13:45 - 15:25)
----------------------------------------

(28)/VLD 13:45 - 14:25
[Invited Talk]
Towards Getting Your Paper Accepted at International Conferences
-- Based on Experiences of Studying Abroad and Serving as a Program Committee Member --
Yuko Hara-Azumi (Tokyo Tech)

(29)/VLD 14:25 - 14:55
[Invited Talk]
Taipei Report
Yasuhiro Takashima (Univ. of Kitakyushu)

(30)/VLD 14:55 - 15:25
[Invited Talk]
EDA Research Activities in The University of Texas at Austin
Tetsuaki Matsunawa (Toshiba)

----------------------------------------
Wed, Dec 2 PM (13:45 - 15:25)
----------------------------------------

(31)/CPSY 13:45 - 14:10
A Preliminary Evaluation of Linear Network Using ThruChip Interface
Akio Nomura, Hiroki Matsutani, Yasuhiro Take (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Technology), Tadahiro Kuroda, Hideharu Amano (Keio Univ.)

(32)/CPSY 14:10 - 14:35
CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture
Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)

(33)/CPSY 14:35 - 15:00
Performance Evaluation of K-best Viterbi Decoder for IoT Applications
Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST)

(34)/RECONF 15:00 - 15:25
Problems that occur in FPGAs communication
-- Cautionary point of PCIe Gen3 --
Hirotaka Takayama, Yoshiki Yamaguchi (Tsukuba Univ.)

----------------------------------------
Wed, Dec 2 PM (13:45 - 15:25)
----------------------------------------

(35)/ICD 13:45 - 14:10
Design of low power AFE circuit supporting IR array sensor for human detection
Shota Ueguchi (Ritsumeikan Univ.), Toshio Kumamoto (Osaka Sangyo Univ.), Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.)

(36)/ICD 14:10 - 14:35
A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique
Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo)

(37)/ICD 14:35 - 15:00
Study on a tolerance for process variability in Single Slope ADC using interpolative TDC
Kaihei Hotta, Kenichi Ohhata (Kagishima Univ.)

(38)/ICD 15:00 - 15:25
EMS Evaluation of Adaptively-Tuned Supply-Resonnace Suppression Filter
Kohki Taniguchi, Noriyuki Miura, Makoto Nagata (Kobe Univ.)

----------------------------------------
Wed, Dec 2 PM (15:25 - 15:55)
----------------------------------------



----------------------------------------
Wed, Dec 2 PM (15:55 - 18:00)
----------------------------------------

(39) 15:55 - 16:20


(40)/VLD 16:20 - 16:45
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)

(41)/VLD 16:45 - 17:10
Layout Decomposition into L-Shaped Parts for Variable Shaped-Beam Mask Writer
Katsuya Hoshi, Kunihiro Fujiyoshi (TUAT)

(42)/VLD 17:10 - 17:35
Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning
Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)

(43)/VLD 17:35 - 18:00
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs
Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

----------------------------------------
Wed, Dec 2 PM (15:55 - 18:00)
----------------------------------------

(44)/ICD 15:55 - 16:20
Dynamic Frame-rate Optimization for Low Energy Object Tracking
Yusuke Inoue, Takatsugu Ono, Koji Inoue (Kyushu Univ.)

(45) 16:20 - 16:45


(46) 16:45 - 17:10


(47)/VLD 17:10 - 17:35
An FPGA implementation of real-time position and pose measurement for robotic head
Masahiro Matsumoto, Kazuhiro Shimonomura (Ritsumeikan)

(48)/RECONF 17:35 - 18:00
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.), Hiroyuki Nakanishi (Kagoshima Univ.), Kazumasa Iwai (NICT), Tohru Nagao (Ehime Univ)

----------------------------------------
Wed, Dec 2 PM (15:55 - 18:00)
----------------------------------------

(49)/VLD 15:55 - 16:20
A low-power soft error tolerant latch scheme on 15nm process
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)

(50)/VLD 16:20 - 16:45
Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)

(51)/CPSY 16:45 - 17:10
An implementation and preliminary evaluation of a dynamic body bias control scheme for a low power micro controller using SOTB MOSFET
Hayate Okuhara (Keio Univ.), Tomoaki Koide (UEC), Johannes maximilian kuehn, Akram Ben Ahmed (Keio Univ.), Koichiro Ishibashi (UEC), Hideharu Amano (Keio Univ.)

(52)/ICD 17:10 - 17:35
The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit
Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP)

(53)/ICD 17:35 - 18:00
An Energy-Autonomous, Disposable Supply-Sensing Biosensor Platform Using Bio Fuel Cell and 0.25μm CMOS 0.23V Ring Oscillator and Proximity Transmitter for Big-Data-Based Healthcare
Kiichi Niitsu (Nagoya Univ./JST), Atsuki Kobayashi, Takashi Ando (Nagoya Univ.), Yudai Ogawa, Matsuhiko Nishizawa (Tohoku Univ.), Kazuo Nakazato (Nagoya Univ.)

----------------------------------------
Thu, Dec 3 AM (09:45 - 10:35)
----------------------------------------

(54)/VLD 09:45 - 10:10
Hardware Trojan Identification based on Netlist Features using SVM
Kento Hasegawa, Oya Masaru, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

(55)/VLD 10:10 - 10:35
A Quantitative Criterion of Gate-Level Netlist Vulnerability
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

----------------------------------------
Thu, Dec 3 AM (09:20 - 10:35)
----------------------------------------

(56)/RECONF 09:20 - 09:45
Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System
Koki Sugi, Tetsushi Koide, Tatsuya Shimizu, Takumi Okamoto, Anh-Tuan Hoang, Hikaru Sato, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Toshida, Hiroshi Mieno (Hiroshima General Hospital), Shinji Tanaka (Hiroshima Univ.)

(57)/RECONF 09:45 - 10:10
Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract
Tatsuya Shimizu, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Takumi Okamoto, Hikaru Sato, Toru Tamaki, Bisser Raytchev, Kazuhumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital), Shinji Tanaka (Hiroshima Univ.)

(58)/RECONF 10:10 - 10:35
High-level synthesis of an image-based human detection FPGA system with a machine learning technique
Ryo Fujita, Masahito Oishi, Yoshiki Hayashida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)

----------------------------------------
Thu, Dec 3 AM (09:20 - 10:35)
----------------------------------------

(59)/DC 09:20 - 09:45
A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)

(60)/VLD 09:45 - 10:10
Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs
Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.)

(61)/VLD 10:10 - 10:35
An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST)

----- Break ( 15 min. ) -----

----------------------------------------
Thu, Dec 3 AM (10:50 - 12:30)
----------------------------------------

(62)/CPM 10:50 - 11:40
[Invited Talk]
Development of Via Structures in IC Package Substrates for Impedance Reduction
Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani (Fujitsu Lab.)

(63)/CPM 11:40 - 12:30
[Invited Talk]
A New Concept of Memory-Logic Conjugated System and It's Spreading
-- Dynamic Reconfiguration System Composed with Memory --
Kanji Otsuka, Youichi Sato (Meisei Univ.), Jun-ichi Kasai (MIRAI)

----------------------------------------
Thu, Dec 3 AM (10:50 - 12:30)
----------------------------------------

(64)/DC 10:50 - 11:15
On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT)

(65)/DC 11:15 - 11:40
Construction and Evaluation of Three-Dimensional Heat Transfer Simulator for LSI Packages
Shougo Watanabe, Takashi Omura, Yuki Kitagawa, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.)

(66)/VLD 11:40 - 12:05
Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)

(67)/VLD 12:05 - 12:30
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

----------------------------------------
Thu, Dec 3 AM (10:50 - 12:30)
----------------------------------------

(68)/CPSY 10:50 - 11:15
Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment
Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.)

(69)/CPSY 11:15 - 11:40
Logic Design of A Single-Flux-Quantum Microprocessor
Koki Ishida, Tomonori Tsuhata (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono, Koji Inoue (Kyushu Univ.)

(70)/CPSY 11:40 - 12:05
Accuracy Analysis of Machine Learning based Performance Modeling for Microprocessors
Yoshihiro Tanaka, Takatsugu Ono, Koji Inoue (Kyushu Univ.)

(71)/CPSY 12:05 - 12:30
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II
Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.)

----- Break ( 75 min. ) -----

----------------------------------------
Thu, Dec 3 PM (13:45 - 15:00)
----------------------------------------

(72)/VLD 13:45 - 14:10
Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)

(73)/VLD 14:10 - 14:35
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)

(74) 14:35 - 15:00


----------------------------------------
Thu, Dec 3 PM (13:45 - 15:25)
----------------------------------------

(75)/DC 13:45 - 14:10
An M by N Algorithm Using Multiple Target Test Generation for Static Test Compaction
Yuya Hara, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon University), Masayoshi Yoshimura (Kyoto Sangyo university)

(76)/DC 14:10 - 14:35
An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.)

(77)/DC 14:35 - 15:00
Design of BIST with soft error resilience for testing FPGAs
Hiroki Ueda, Daichi Shimadu, Satoshi Ohtake (Oita univ.)

(78)/DC 15:00 - 15:25
Easily-testable Carry Select Adder with Online Error Detection Capability
Nobutaka Kito (Chukyo Univ.)

----------------------------------------
Thu, Dec 3 PM (13:45 - 15:25)
----------------------------------------

(79)/VLD 13:45 - 14:10
Fast and Accurate Estimation of Execution Cycles for ARM Architecture
Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ)

(80)/VLD 14:10 - 14:35
Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement
Junya Goto, Nagisa Ishiura (K.G.)

(81)/VLD 14:35 - 15:00
Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses
Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.)

(82)/VLD 15:00 - 15:25
A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Tue, Jan 19, 2016 - Thu, Jan 21, 2016: Hiyoshi Campus, Keio University [Mon, Nov 2], Topics: FPGA Applications, etc

# SECRETARY:
Kazuya Tanigawa
Hiroshima City University,
e-mail: tanigawa@hiroshima-cu.ac.jp

=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Tue, Jan 19, 2016 - Thu, Jan 21, 2016: Hiyoshi Campus, Keio University [Mon, Nov 2], Topics: FPGA Applications, etc
Mon, Feb 29, 2016 - Wed, Mar 2, 2016: Okinawa Seinen Kaikan [Fri, Jan 15]

# SECRETARY:
Hiroyuki Tomiyama (Ritsumeikan University)
E-mail: ht@fc.ritsumei.ac.jp
Phone: 077-561-4928

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Technical Committee on Component Parts and Materials (CPM) ===

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Dec 17, 2015 - Fri, Dec 18, 2015: Kyoto Institute of Technology [Mon, Nov 2]
Tue, Mar 1, 2016 - Wed, Mar 2, 2016 (tentative): [unfixed]
Wed, Mar 2, 2016 - Fri, Mar 4, 2016: Hiroshima University [Mon, Jan 18], Topics: Microwave Integrated Circuit / Microwave Technologies

# SECRETARY:
橋本 隆(パナソニック)
TEL 06-6905-5950
E-mail:hashimoto.takashi1967@jp.panasonic.com

岩崎 裕江(NTT)
TEL 046-859-3102
E-mail:iwasaki.hiroe@lab.ntt.co.jp

=== Technical Committee on Computer Systems (CPSY) ===
# FUTURE SCHEDULE:

Thu, Dec 17, 2015 - Fri, Dec 18, 2015: Kyoto Institute of Technology [Mon, Nov 2]
Tue, Jan 19, 2016 - Thu, Jan 21, 2016: Hiyoshi Campus, Keio University [Mon, Nov 2], Topics: FPGA Applications, etc
Thu, Mar 24, 2016 - Fri, Mar 25, 2016: Fukue Bunka Hall/Rodou Fukushi Center [Wed, Jan 13], Topics: ETNET2016

# SECRETARY:
Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-mail: miyoshi.takashi@jp.fujitsu.com

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/

=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:

Fri, Dec 18, 2015: Kurieito Mulakami (Murakami City) [Fri, Oct 16]
Wed, Feb 17, 2016: Kikai-Shinko-Kaikan Bldg. [Fri, Dec 11], Topics: VLSI Design and Test, etc.
Thu, Mar 24, 2016 - Fri, Mar 25, 2016: Fukue Bunka Hall/Rodou Fukushi Center [Wed, Jan 13], Topics: ETNET2016

# SECRETARY:


=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:

Tue, Jan 19, 2016 - Thu, Jan 21, 2016: Hiyoshi Campus, Keio University [Mon, Nov 2], Topics: FPGA Applications, etc
Thu, Mar 24, 2016 - Fri, Mar 25, 2016: Fukue Bunka Hall/Rodou Fukushi Center [Wed, Jan 13], Topics: ETNET2016

# SECRETARY:
Yasuhiro Takashima (University of Kitakyushu)
Email sldm2015@is.env.kitakyu-u.ac.jp

# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


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