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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) Secretary: Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Yohei Hori (Chuo Univ.) DATE: Thu, May 14, 2009 13:00 - 17:50 Fri, May 15, 2009 09:30 - 15:50 PLACE: TOPICS: ---------------------------------------- Thu, May 14 PM (13:00 - 15:00) ---------------------------------------- (1) 13:00 - 13:30 Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension Ken'ichi Umeda, Takuro Uchida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) (2) 13:30 - 14:00 Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) (3) 14:00 - 14:30 Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs Sen In, Hiroki Matsutani, Daihang Wang (Keio Univ), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ) (4) 14:30 - 15:00 A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network Shoichi Nishida (Kumamoto Univ.), Yuzo Nishioka (Hitachi-Omron Terminal Solutions, Corp.), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 14 PM (15:10 - 16:40) ---------------------------------------- (5) 15:10 - 15:40 Proposal and Implementation of High Throughput Algorithm for Combination Generation Akira Tsuji, Norio Yamagaki, Satoshi Kamiya (NEC) (6) 15:40 - 16:10 Accelerating HMMER search using FPGA Toyokazu Takagi, Tsutomu Maruyama (Univ. of Tsukuba) (7) 16:10 - 16:40 Performance evaluation of an auto-generation algorithm of hardware modules for an FPGA-based general-purpose biochemical simulator Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata (Nagasaki Univ), Yasunori Osana (Seikei Univ), Masato Yoshimi (Doshisha Univ), Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi (Keio Univ), Kiyoshi Oguri (Nagasaki Univ) ----- Break ( 20 min. ) ----- ---------------------------------------- Thu, May 14 PM (17:00 - 17:50) ---------------------------------------- (8) 17:00 - 17:50 [Invited Talk] Development of Interactive Supercomputing Environment Shin-ichiro Mori (Univ. of Fukui), Tomohiro Kuroda, Naoto Kume (Kyoto Univ.), Yoshihiro Kuroda (Osaka Univ.), Megumi Nakao, Hajime Shimada, Yasuhiko Nakashima (NAIST), Shinji Tomita (Kyoto Univ.) ----- Party ( 120 min. ) ----- ---------------------------------------- Fri, May 15 AM (09:30 - 11:30) ---------------------------------------- (9) 09:30 - 10:00 Recovery and syncronization technique for TMR softcore processor Yoshihiro Ichinomiya, Shiro Tanoue, Toshio Yabuta, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (10) 10:00 - 10:30 A low-power clustering tool using both routability and activity for FPGAs Junya Eto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (11) 10:30 - 11:00 A Memory Access Optimization Method for Reconfigurable Systems Based on a Multithread Programming Model Keisuke Dohi, Sayaka Shida, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.) (12) 11:00 - 11:30 Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis Yohei Hori, Mai Itoh (Chuo Univ.), Hideki Imai (Chuo Univ./AIST) ----- Lunch Break ( 70 min. ) ----- ---------------------------------------- Fri, May 15 PM (12:40 - 14:10) ---------------------------------------- (13) 12:40 - 13:10 * Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.) (14) 13:10 - 13:40 Real-time processing of local contrast enhancement on FPGA Kentaro Kokufuta, Tsutomu Maruyama (Univ. of Tsukuba) (15) 13:40 - 14:10 Performance comparison of GPU and FPGA in image processing Shuichi Asano, Tsutomu Maruyama (Univ. of Tsukuba) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, May 15 PM (14:20 - 15:50) ---------------------------------------- (16) 14:20 - 14:50 A comparative study of implementing N-body simulation on FPGAs, GPUs and general purpose processors Tsuyoshi Hamada (Nagasaki Univ), Khaled Benkrid (Univ. of Edinburgh), Kiego Nitadori (RIKEN), Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) (17) 14:50 - 15:20 Modularizing Flux Limiter Functions in UPACS for CFD Accelerator FLOPS-2D Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) (18) 15:20 - 15:50 Acceleration of UPACS subroutines with FPGAs Takaaki Yokoyama, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Yohei HORI (Chuo Univ.) E-mail:   -y i ab  TEL: +81-3-3817-1631 FAX: +81-3-3817-1855 Last modified: 2009-05-10 11:47:15 |
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