===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Minoru Watanabe (Shizuoka Univ.)
Vice Chair: Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.)
Secretary: Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant: Kazuya Tanikagawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
DATE:
Fri, Jun 19, 2015 10:00 - 20:00
Sat, Jun 20, 2015 09:30 - 18:30
PLACE:
Clock Tower Centennial Hall, Kyoto University(Clock Tower Centennial Hall, Kyoto University Yoshida-Honmachi, Sakyo-ku, Kyoto, 606-8501. 5 minutes walk from Kyo-dai 'Sei-mon-mae' bus stop. http://www.kyoto-u.ac.jp/en/access/yoshida/main.html. Tomonori Izumi (Ritsumeikan Univ.) / Masayuki Hiromoto (Kyoto Univ.))
TOPICS:
the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc.
----------------------------------------
Fri, Jun 19 AM Special Invited Talk (10:00 - 11:00)
Chair: Tetsuo Hironaka （Hiroshima City Univ.)
----------------------------------------
(1) 10:00 - 11:00
[Special Talk]
Semiconductor Innovation seen from Makimoto's Wave and its Impact
Tsugio Makimoto (SSIS)
----- Break ( 10 min. ) -----
----------------------------------------
Fri, Jun 19 AM Architecture and performance assessment (1) (11:10 - 13:20)
Chair: Nobuya WATANABE (Okayama Univ.)
----------------------------------------
(2) 11:10 - 11:35
Power optimization of low-power reconfigurable accelerator CMA-SOTB
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano (Keio Univ.)
(3) 11:35 - 12:00
Evaluation of the third Flex Power FPGA chip in SOTB technology
Masakazu Hioki, Yasuhiro Ogasahara, Hanpei Koike (AIST)
(4) 12:00 - 12:25
An Area Optimization of 3D FPGA with high speed inter-layer communication link
Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
----- lunch ( 55 min. ) -----
----------------------------------------
Fri, Jun 19 PM Image Processing (13:20 - 15:00)
Chair: Hideharu AMANO (Keio Univ.)
----------------------------------------
(5) 13:20 - 13:45
A Classification Hardware with Hierarchical Multiple Scan Window Sizes for Colorectal Endoscopic Diagnosis
Takumi Okamoto, Tetsushi Koide, Tatsuya Shimizu, Koki Sugi, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.)
(6) 13:45 - 14:10
Consideration for Visual Word Feature Transformation Hardware based on Bag-of-Features
Koki Sugi, Tetsushi Koide, Tatsuya Shimizu, Takumi Okamoto, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.)
(7) 14:10 - 14:35
High Speed Calculation of Convex Hull in 2D Images using FPGA
Kahori Kemmotsu, Kenji Kanazawa, Yamato Mori (Univ. of Tsukuba), Noriyuki Aibe (SUSUBOX), Moritoshi Yasunaga (Univ. of Tsukuba)
(8) 14:35 - 15:00
ROS compliant componentizing of image processing hardware on a Programmable SoC
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
----- Break ( 10 min. ) -----
----------------------------------------
Fri, Jun 19 PM FPGA Applications, etc (1) (15:10 - 16:50)
Chair: Kentaro SANO (Tohoku Univ.)
----------------------------------------
(9) 15:10 - 15:35
Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA
Keisuke Hirofuji, Ryo Okuda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
(10) 15:35 - 16:00
Realization of FPGA Control Processing with Functional Safety
Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Yudai Shirakura, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
(11) 16:00 - 16:25
An arithmetic design approach with diversity and redundancy for FPGAs
Yudai Shirakura, Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
(12) 16:25 - 16:50
Towards the Fastest FPGA-based Sorting Hardware in the World
Ryohei Kobayashi, Kenji Kise (Tokyo Tech)
----- Break ( 10 min. ) -----
----------------------------------------
Fri, Jun 19 PM Invited talk (17:00 - 18:00)
Chair: Yuichiro SHIBATA (Nagasaki Univ.)
----------------------------------------
(13) 17:00 - 18:00
[Invited Talk]
Reliability on Integrated Circuits
Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
----------------------------------------
Fri, Jun 19 PM (18:00 - 20:00)
Chair: Yoshiki YAMAGUCHI (Univ. of Tsukuba)
----------------------------------------
(14) 18:00 - 20:00
----------------------------------------
Sat, Jun 20 AM FPGA Applications, etc (2) (09:30 - 10:45)
Chair: Takefumi Miyoshi (e-trees.Japan)
----------------------------------------
(15) 09:30 - 09:55
A SW/HW Interface Implementation Method in the System Design Environment for Programmable SoCs
Yusuke Tani, Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
(16) 09:55 - 10:20
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications
Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
(17) 10:20 - 10:45
Implementation and Applications of An Efficient Parallel Architecture for Matrix Calculations
Yuki Murakami, Naohito Nakasato, S. Sedukhin (Univ. of Aizu)
----------------------------------------
Sat, Jun 20 AM FPGA Applications, etc (3) (10:45 - 13:10)
Chair: Moritoshi YASUNAGA (Univ. of Tsukuba)
----------------------------------------
(18) 10:45 - 11:10
A Deep Convolutional Neural Network Based on Nested Residue Number System
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.)
(19) 11:10 - 11:35
A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST)
(20) 11:35 - 12:00
FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3
Yohei Hori, Toshihiro Katashita (AIST)
----- Meeting (Technical Committee on RECONF) ( 70 min. ) -----
----------------------------------------
Sat, Jun 20 PM FPGA Design Contest (13:10 - 13:35)
Chair: Hiroki Nakahara (Ehime Univ.)
----------------------------------------
(21) 13:10 - 13:35
Introduction to 2015 FPGA Trax contest
Yasunori Osana (Univ. of the Ryukyus), Tomonori Izumi (Ritsmeikan Univ.), Takefumi Miyoshi (e-trees), Hiroki Nakahara (Ehime Univ.)
----------------------------------------
Sat, Jun 20 PM Architecture and performance assessment (2) (13:35 - 15:15)
Chair: Masahiro IIDA (Kumamoto Univ.)
----------------------------------------
(22) 13:35 - 14:00
Real Chip evaluation of a dynamically reconfigurable processor MuCCRA-4 with ST micro 28nm Process
Hideharu Amano, Toru Katagiri (Keio Univ.)
(23) 14:00 - 14:25
On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors
Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST)
(24) 14:25 - 14:50
Tile-base PLA Cell with Uni-Switch Structure
Atsushi Nanri, Kosuke Murakami, Daijiro Murooka, Takuya Hirata, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)
(25) 14:50 - 15:15
High-speed scrubbing on optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
----- Break ( 10 min. ) -----
----------------------------------------
Sat, Jun 20 PM Architecture and performance assessment (3) (15:25 - 17:05)
Chair: Minoru Watanabe (Shizuoka Univ.)
----------------------------------------
(26) 15:25 - 15:50
Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch
Naoya Tokusada, Tetsuo Hironaka, Kazuya Tanigawa (HCU), Takashi Ishiguro (Taiyo Yuden)
(27) 15:50 - 16:15
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device
Tieyuan Pan, Zhu Li, Lian Zeng, Takahiro Watanabe (Waseda Univ.), Yasuhiro Takashima (Univ. of Kitakyushu)
(28) 16:15 - 16:40
A Technology Mapping Method for Scalable Logic Module
Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
(29) 16:40 - 17:05
Data-Triggered Breakpoint for In-Circuit Debug without Re-implementation
Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura (Fujitsu Labs.)
----- Break ( 10 min. ) -----
----------------------------------------
Sat, Jun 20 PM FPGA Applications, etc (4) (17:15 - 18:30)
Chair: Kazuya Tanigawa （Hiroshima City Univ.)
----------------------------------------
(30) 17:15 - 17:40
High-Level Synthesis Compiler for Hierarchical and Modular Design of Stream Computing Cores
Kentaro Sano, Ryo Ito, Keisuke Sugawara, Satoru Yamamoto (Tohoku Univ.)
(31) 17:40 - 18:05
An Implementation and Evaluation of A Generic Interface between PC and FPGA with AHCI
Takefumi Miyoshi, Satoshi Funada (e-trees)
(32) 18:05 - 18:30
FPGA design using high-level description
-- sound synthesizer implementation and its evaluation --
Fang-Xiang Gao, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. Tsukuba)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
Special Invited Talk will have 50 minutes for presentation and 10 minutes for discussion.
Invited Talk will have 50 minutes for presentation and 10 minutes for discussion.
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:
Fri, Sep 18, 2015 - Sat, Sep 19, 2015 (tentative): Ehime University [Mon, Jul 20], Topics: Reconfigurable Systems, etc.
# SECRETARY:
Yoshiki YAMAGUCHI
University of Tsukuba
e-mail: yoshiki [at] cs.tsukuba.ac.jp
Last modified: 2015-05-11 12:53:09
|
Notification: Mail addresses are partially hidden against SPAM.
|