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Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Yoshinobu Maeda (Niigata Univ.)
Vice Chair Yasutoshi Aibara (OmniVisionManufacturing)
Secretary Nao Ito (NIT, Toyama college), Hiroto Suzuki (Renesas)
Assistant Motoi Yamaguchi (TECHNOPRO), Yohei Nakamura (Hitachi), Takahide Sato (Univ. of Yamanashi), Shinji Shimoda (Sony LSI Design), Shunsuke Koshita (Hachinohe Inst. of Tech.)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Vice Chair Minako Ikeda (NTT)
Secretary Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Yukihiro Bandou (NTT)
Vice Chair Toshihisa Tanaka (Tokyo Univ. Agri.&Tech.), Takayuki Nakachi (Ryukyu Univ.)
Secretary Kenjiro Sugimoto (Xiaomi), Osamu Watanabe (Takushoku Univ.), Yuichi Tanaka (Tokyo Univ. Agri.&Tech.)
Assistant Taichi Yoshida (UEC), Seisuke Kyochi (Univ. of Kitakyushu)

Technical Committee on Mathematical Systems Science and its Applications (MSS) [schedule] [select]
Chair Atsuo Ozaki (Osaka Inst. of Tech.)
Vice Chair Shingo Yamaguchi (Yamaguchi Univ.)
Secretary Koichi Kobayashi (Hokkaido Univ.), Jianquan Liui (NEC)
Assistant Masato Shirai (Shimane Univ.)

Conference Date Thu, Jun 16, 2022 10:00 - 17:50
Fri, Jun 17, 2022 10:00 - 16:10
Topics  
Conference Place  
Sponsors This conference is co-sponsored by IEEE Signal Processing Society Tokyo Joint Chapter. This conference is technical co-sponsored by IEEE Circuits and Systems Society Japan Chapter（IEEE CASS JC）, IEEE Signal Processing Society Tokyo Joint Chapter and APSIPA Japan Chapter.
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CAS, SIP, VLD, MSS.

Thu, Jun 16 AM 
10:00 - 11:40
(1) 10:00-10:25 Path Planning of Heterogeneous Multi-robot Systems Satisfying a Counting Temporal Logics Constraint Kotaro Nagae, Toshimitsu Ushio (Osaka Univ.)
(2) 10:25-10:50 Equal Opportunity in Robust Optimization for Unit Commitment Problem Considering Suppression of Renewable Energy Ichiro Toyoshima (TOSHIBA ESS), Pierre-Louis Poirion (RIKEN AIP), Tomohide Yamazaki, Kota Yaguchi, Masayuki Kubota, Ryota Mizutani (TOSHIBA ESS), Akiko Takeda (The University of Tokyo)
(3) 10:50-11:15 Multi-Agent Surveillance Based on Equitability of Travel Costs Kyohei Murakata, Koichi Kobayashi, Yuh Yamashita (Hokkaido Univ.)
(4) 11:15-11:40 A Peer-to-Peer Energy Trading Model for Optimizing both Efficiency and Fairness Eiichi Kusatake, Norihiko Shinomiya (Soka Univ.)
  11:40-13:00 Break ( 80 min. )
Thu, Jun 16 PM 
13:00 - 14:00
(5) 13:00-14:00 [Special Invited Talk]
Progress of RF Circuits and Mixed RF Analog-Digital Circuits for Mobile Communication Terminals 		Satoshi Tanaka (Murata Manufacturing)
  14:00-14:15 Break ( 15 min. )
Thu, Jun 16 PM 
14:15 - 15:55
(6) 14:15-14:40 Access control of ConvMixer models based on patch embedding structure Ryota Iijima, Hitoshi Kiya (Tokyo Metro. Univ.)
(7) 14:40-15:05 Adversarial Robustness of Secret Key-Based Defenses against AutoAttack Miki Tanaka, April Pyone MaungMaung (Tokyo Metro Univ.), Isao Echizen (NII), Hitoshi Kiya (Tokyo Metro Univ.)
(8) 15:05-15:30 Image Classification Using Vision Transformer for Compressible Encrypted Images Genki Hamano, Shoko Imaizumi (Chiba Univ.), Hitoshi Kiya (Tokyo Metropolitan Univ.)
(9) 15:30-15:55 Trajectory Classification Based on Correlation Coefficient Comparison for Background Subtraction with Moving Cameras Ryosuke Isono (Tokyo Tech.), Ryo Hayakawa, Youji Iiguni (Osaka Univ.)
  15:55-16:10 Break ( 15 min. )
Thu, Jun 16 PM 
16:10 - 16:35
(10) 16:10-16:35 Dynamic Temperature Control Algorithm for 3-D Stacked Chips based on Thermal Analysis Songxiang Wang, Kimiyoshi Usami (Shibaura IT)
  16:35-16:50 Break ( 15 min. )
Thu, Jun 16 PM 
16:50 - 17:50
(11) 16:50-17:50  
Fri, Jun 17 AM 
10:00 - 11:30
(12) 10:00-11:30 [Panel Discussion]
Contributions of System and Signal Processing Subsociety to the SDGs 		Shigemasa Takai (Osaka Univ.), Yoshinobu Maeda (Niigata Univ.), Namiko Ikeda (NTT), Toshihisa Tanaka (TUAT), Atsuo Ozaki (OIT)
  11:30-13:00 Break ( 90 min. )
Fri, Jun 17 PM 
13:00 - 14:40
(13) 13:00-13:25 A revised shortest path-based routing in WSN model Yoshihiro Kaneko (Gifu Univ.), Mayu Okumura (Meitec)
(14) 13:25-13:50 An Attempt to Design an Artificial School Class Game That Introduces a Teacher's Perspective Ryuto Ogata, Hidenori Kondo (Niigata Univ.), Kentaro Tani, Takahisa Kamikura (Niigata University of Health and Welfare), Takumi Akatsuka (Rounexy Corp.), Tsunehiko Tanaka, Tatsuya Yamazaki, Yoshinobu Maeda (Niigata Univ.)
(15) 13:50-14:15 Improvement of the accuracy for Ultra Wide Band indoor position estimation by modified state transition model for Particle Filter Fukagawa Minoru, Unjo Kazuya, Ito Nao (NIT-Toyama)
(16) 14:15-14:40 Important Roles of Heaviside's Expansion Theorem for Electromagnetic Phenomena Nobuo Nagai (Hokkaido Univ.), Takashi Yahagi (RISP)
  14:40-14:55 Break ( 15 min. )
Fri, Jun 17 PM 
14:55 - 16:10
(17) 14:55-15:20 Construction of scoring probability model based on service landing location and ranking points in men's professional tennis matches Fumiya Shimizu, Eiji Konaka (Meijo Univ.)
(18) 15:20-15:45 Petri Net-based QUBO Model Formulation for Flow Shop Scheduling with Setup Changes Takuya Shinjo, Morikazu Nakamura (Univ. of the Ryukyus), Norihiko Itani (Fujitsu Ltd.)
(19) 15:45-16:10 QUBO Model Formulation based on Petri net Behavior for Combinatorial Optimization Problems Keisuke Tokuhira, Morikazu Nakamura, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address CAS administrator Group
E--mail: cas-adn 
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Daisuke KANEMOTO (Osaka Univ. )
E--mail: deeieng-u 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address IEICE Technical Group on Signal Processing
Email: sip-n 
MSS Technical Committee on Mathematical Systems Science and its Applications (MSS)   [Latest Schedule]
Contact Address Koichi Kobayashi (Hokkaido University)
Tel: +81-11-706-6452
E--mail: k-bassiisti 


Last modified: 2022-06-13 19:29:33


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