Mon, May 22 PM Neural Network Accelerator
14:00 - 15:00 |
(1)
RECONF |
14:00-14:20 |
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(2)
RECONF |
14:20-14:40 |
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(3)
RECONF |
14:40-15:00 |
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15:00-15:10 |
Break ( 10 min. ) |
Mon, May 22 PM Invited Talk 1
15:10 - 15:50 |
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15:10-15:50 |
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15:50-16:00 |
Break ( 10 min. ) |
Mon, May 22 PM Neural Network Application on FPGAs
16:00 - 17:00 |
(5)
RECONF |
16:00-16:20 |
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(6)
RECONF |
16:20-16:40 |
CNN implementation on FPGA with Power of 2 Approximation of Weight |
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(7)
RECONF |
16:40-17:00 |
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17:00-17:10 |
Break ( 10 min. ) |
Mon, May 22 PM Reconfigurable LSI
17:10 - 18:10 |
(8)
RECONF |
17:10-17:30 |
A proposal of Bit Serial Arithmetic Units for Arbitrary Precision |
Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(9)
RECONF |
17:30-17:50 |
Radiation tolerance of a holographic memory for optically reconfigurable gate arrays |
Yoshizumi Ito, Minoru Watanabe (Shizuoka Univ.), Akifumi Ogiwara (Kobe City College of Tech.) |
(10)
RECONF |
17:50-18:10 |
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Tue, May 23 AM Image Processing Application on FPGAs
09:00 - 10:00 |
(11)
RECONF |
09:00-09:20 |
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(12)
RECONF |
09:20-09:40 |
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Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science) |
(13)
RECONF |
09:40-10:00 |
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10:00-10:15 |
Break ( 15 min. ) |
Tue, May 23 AM Algorithm and Reconfigurable Device
10:15 - 11:15 |
(14)
RECONF |
10:15-10:35 |
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(15)
RECONF |
10:35-10:55 |
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(16)
RECONF |
10:55-11:15 |
Power Optimization for Pipelined CGRA with Intger Linear Program |
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng.Doan Anh Vu, Hideharu Amano (Keio Univ.) |
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11:15-11:30 |
Break ( 15 min. ) |
Tue, May 23 AM FPGA Application and Acceleration System
11:30 - 12:30 |
(17)
RECONF |
11:30-11:50 |
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(18)
RECONF |
11:50-12:10 |
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(19)
RECONF |
12:10-12:30 |
FPGA and DPDK-Based Communication Acceleration Methods for Parameter Servers |
Kazumasa Kishiki, Korechika Tamura, Hiroki Matsutani (Keio Univ.) |
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12:30-14:00 |
Break ( 90 min. ) |
Tue, May 23 PM Light Application
14:00 - 15:00 |
(20)
RECONF |
14:00-14:20 |
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(21)
CPSY |
14:20-14:40 |
A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems |
Duc Phuc Nguyen, Dinh Dung Le, Thi Hong Tran, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
(22)
CPSY |
14:40-15:00 |
A prototype of Dimmable Visible Light Communication System on FPGA |
Dinh Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima (NAIST), Son Kiet Nguyen, Huu Thuan Huynh (HCMUS) |
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15:00-15:10 |
Break ( 10 min. ) |
Tue, May 23 PM Invited Talk 2
15:10 - 15:50 |
| (23) |
15:10-15:50 |
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15:50-16:00 |
Break ( 10 min. ) |
Tue, May 23 PM Bud Flush Architecture
16:00 - 17:00 |
(24)
CPSY |
16:00-16:20 |
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(25)
CPSY |
16:20-16:40 |
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Hisakazu Fukuoka, Ryusuke Yamano, Yasuhiko Nakashima (NAIST) |
(26)
CPSY |
16:40-17:00 |
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17:00-17:10 |
Break ( 10 min. ) |
Tue, May 23 PM Algorithm
17:10 - 18:10 |
(27)
CPSY |
17:10-17:30 |
A Case for HTM-supported Concurrent B-trees |
Kousei Sai, Jun Miyazaki (Tokyo Inst. of Tech.) |
(28)
CPSY |
17:30-17:50 |
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(29)
CPSY |
17:50-18:10 |
Optimization of the aggregation process in Particle-In-Cell method using OpenCL |
Hiroyuki Noda, Ryotaro Sakai (Keio Univ.), Takaaki Miyajima, Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) |
Wed, May 24 AM Distributed System
09:00 - 10:00 |
(30)
CPSY |
09:00-09:20 |
Deduplication Estimation System for Large Scale Enterprise Storage |
Kazuei Hironaka, Tomohiro Kawaguchi (Hitachi) |
| (31) |
09:20-09:40 |
パケット処理キャッシュにおける送信元IPアドレスに着目したミス削減手法に関する初期検討
○八巻 隼人、愛甲 達也、三輪 忍、本多 弘樹（電気通信大学） |
(32)
CPSY |
09:40-10:00 |
A Concept for Distributed Neural Network on Edge Computing |
Yuria Hiraga, Takamasa Mitani, Hisakazu Fukuoka, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
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10:00-10:15 |
Break ( 15 min. ) |
Wed, May 24 AM Dependable Computing
10:15 - 11:15 |
(33)
DC |
10:15-10:35 |
Deterministic Path Delay Measurement Using Short Cycle Test Pattern for Aging Detection |
Kentaro Kato, Umi Mori (NIT) |
(34)
DC |
10:35-10:55 |
On Implementation of the Light-Weight MPAR protocol in NS2 |
Yusuke Sugiura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
(35)
DC |
10:55-11:15 |
Study on Application System Anomaly Detection Method Based on Correlation Analysis of Communication Packets Sampling |
Masahiko Yasui, Masayuki Sakata, Keisuke Hatasaki, Keitaro Uehara, Takaya Ide, Hitoshi Yabusaki (Hitachi) |
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11:15-11:30 |
Break ( 15 min. ) |
Wed, May 24 AM Microarchitecture
11:30 - 12:30 |
| (36) |
11:30-11:50 |
低電力モードを備えるプロセッサとモード切り替えアルゴリズムによる電力効率の向上
○塩谷 亮太、地代 康政、出岡 宏二郎（名古屋大学）、五島 正裕（国立情報学研究所）、安藤 秀樹（名古屋大学） |
| (37) |
11:50-12:10 |
動的タイム・ボローイングを可能にするクロッキング方式のスカラ・プロセッサへの適用
○神保 潮（総合研究大学院大学）、五島 正裕（国立情報学研究所） |
(38)
DC |
12:10-12:30 |
Note on Evaluation Scheme for Redundant CPU Cache Considering Soft Error Resilience and Performance |
Naoya Kawashima, Masayuki Arai (Nihon Univ.) |
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