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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Akihisa Yamada (Sharp)
Vice Chair Makoto Ikeda (Univ. of Tokyo)
Secretary Takashi Takenaka (NEC), Shigetoshi Nakatake (Univ. of Kitakyushu)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Yasuji Ota (Fujitsu)
Vice Chair Hiroshi Sawada (NTT), Yoshinobu Kajikawa (Kansai Univ.)
Secretary Takeshi Otani (Fujitsu Labs.), Keisuke Kinoshita (NTT)
Assistant Takanobu Nishiura (Ritsumeikan Univ.)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Masahiko Yoshimoto (Kobe Univ.)
Vice Chair Takeshi Yamamura (Fujitsu Labs.)
Secretary Toshimasa Matsuoka (Osaka Univ.), Ken Takeuchi (Chuo Univ.)
Assistant Osamu Watanabe (Toshiba), Shinichi Ouchi (AIST), Akira Tsuchiya (Kyoto Univ.)

Technical Committee on Image Engineering (IE) [schedule] [select]
Chair Hirohisa Jozawa (NTT)
Vice Chair Toshiaki Fujii (Nagoya Univ.), Kazuhisa Iguchi (NHK)
Secretary Sei Naito (KDDI R&D Labs.), Akira Kubota (Chuo Univ.)
Assistant Takayuki Hamamoto (Tokyo Univ. of Science), Yukihiro Bandoh (NTT-AT)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Michiaki Muraoka
Secretary Hiroaki Komatsu (Fujitsu), Naoki Iwata, Nozomu Togawa (Waseda Univ.)

Conference Date Thu, Oct 18, 2012 13:30 - 17:00
Fri, Oct 19, 2012 09:00 - 16:50
Topics  
Conference Place  
Contact
Person
岩手県立大学
Sponsors This conference is co-sponsored by IEEE Signal Processing Society Japan Chapter and IEEE SSCS Japan/Kansai Chapter.
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Thu, Oct 18 PM 
13:30 - 14:45
(1) 13:30-13:55 Human Behavior Detection Using Direction Change Invariant Features of Cubic Higher Order Local Auto Correlation VLD2012-40 SIP2012-62 ICD2012-57 IE2012-64 Takeyuki Ishii, Hitomi Murakami, Atsushi Koike (Seikei Univ.)
(2) 13:55-14:20 Avoiding Error Magnification in Weighted Median Cut Quantization in Decoding Process
-- High Quality Data Compression of Sparse Histogram Images --
VLD2012-41 SIP2012-63 ICD2012-58 IE2012-65
Toru Ikarashi, Masahiro Iwahashi (Nagaoka Univ. of Tech.), Hitoshi Kiya (Tokyo Metropolitan Univ.)
(3) 14:20-14:45 A Design of Hilbert Transformers using an L1 error criterion VLD2012-42 SIP2012-64 ICD2012-59 IE2012-66 Ikuya Murakami, Naoyuki Aikawa (Tokyo Univ. of Science)
  14:45-15:00 Break ( 15 min. )
Thu, Oct 18 PM 
15:00 - 15:50
(4) 15:00-15:25 A 16-gray-scale image recognition on a dynamically reconfigurable vision architecture VLD2012-43 SIP2012-65 ICD2012-60 IE2012-67 Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.)
(5) 15:25-15:50 Learning of shade for beginners based on interactive pencil-drawing learning support system using tablet PC VLD2012-44 SIP2012-66 ICD2012-61 IE2012-68 Akihiro Sawada, Masashi Kameda (Iwate City Univ.)
  15:50-16:00 Break ( 10 min. )
Thu, Oct 18 PM 
16:00 - 17:00
(6) 16:00-17:00 [Invited Talk]
Computing Technologies for Human-Centered Real-World Intelligent Systems VLD2012-45 SIP2012-67 ICD2012-62 IE2012-69
Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
Fri, Oct 19 AM 
09:00 - 10:40
(7) 09:00-09:25 Power consumption analysis of a mono instruction set computer architecture VLD2012-46 SIP2012-68 ICD2012-63 IE2012-70 Hiroyuki Ito, Minoru Watanabe (Shizuoka Univ.)
(8) 09:25-09:50 Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.)
(9) 09:50-10:15 Design of Stochastic Flash A/D Converter using a non-linearity calibration technique VLD2012-48 SIP2012-70 ICD2012-65 IE2012-72 Shinya Yano, Hyunju Ham, Toshimasa Matsuoka, Jun Wang, Ikkyun Jo (Osaka Univ.)
(10) 10:15-10:40 A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage VLD2012-49 SIP2012-71 ICD2012-66 IE2012-73 Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.)
  10:40-11:00 Break ( 20 min. )
Fri, Oct 19 AM 
11:00 - 12:00
(11) 11:00-12:00 [Invited Talk]
Development of Heterogeneous Multi-Core SoC ViscontiTM2 for Image Recognition Applications VLD2012-50 SIP2012-72 ICD2012-67 IE2012-74
Takashi Miyamori, Yasuki Tanabe, Moriyasu Banno (Toshiba)
  12:00-13:00 Break ( 60 min. )
Fri, Oct 19 PM 
13:00 - 14:15
(12) 13:00-13:25 Accelerator Architecture for Multi Scale Filter Operation VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
(13) 13:25-13:50 Load buffer with conversion capability from tiled data to raster data for motion search VLD2012-52 SIP2012-74 ICD2012-69 IE2012-76 Takumi Inomata, Atsushi Tachino, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)
(14) 13:50-14:15 A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A2BC) Motion Estimation Algorithm VLD2012-53 SIP2012-75 ICD2012-70 IE2012-77 Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo Univ)
  14:15-14:30 Break ( 15 min. )
Fri, Oct 19 PM 
14:30 - 15:45
(15) 14:30-14:55 CMOS Op-amp Circuit Synthesis with Geometric Programming VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78 Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.)
(16) 14:55-15:20 Fast Estimation of Dynamic Delay Distribution VLD2012-55 SIP2012-77 ICD2012-72 IE2012-79 Dai Akita, Kenta Ando (Osaka Univ.), Atsushi Takahashi (Tokyo Tech.)
(17) 15:20-15:45 Reduction of array accesses with WAR dependencies VLD2012-56 SIP2012-78 ICD2012-73 IE2012-80 Takayuki Ookawa, Kenshu Seto (Tokyo City Univ.)
  15:45-16:00 Break ( 15 min. )
Fri, Oct 19 PM 
16:00 - 16:50
(18) 16:00-16:25 Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit   VLD2012-57 SIP2012-79 ICD2012-74 IE2012-81 Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(19) 16:25-16:50 Write Reduction for Non-volatile Registers Using the Max-flow Min-cut Theorem VLD2012-58 SIP2012-80 ICD2012-75 IE2012-82 Yudai Itoi, Shinji Kimura (Waseda Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Takeshi Takenaka (NEC)
E--mail: ajc
Tel: 044-431-7194 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address  
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Minoru Fujishima (The University of Tokyo)
TEL 03-5841-7425,FAX 03-5841-8575
E--mail:eetu- 
IE Technical Committee on Image Engineering (IE)   [Latest Schedule]
Contact Address Akira Kubota (Chuo Univ.)
E--mail: ie-n2012 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Nozomu Togawa (Waseda University)
Email sldm2012g 


Last modified: 2012-10-08 10:31:50


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