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=============================================== Special Interest Group on Computer Architecture (IPSJ-ARC) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Hirofumi Hamamura Vice Chair: Nagisa Ishiura Secretary: Toshiyuki Shibuya, Hiroyuki Ochi =============================================== Technical Committee on Computer Systems (CPSY) Chair: Takanobu Baba Vice Chair: Nobuki Kajihara, Toshinori Sueyoshi Secretary: Hiroko Midorikawa, Akira Asato Assistant: Takashi Yokota =============================================== Technical Committee on Dependable Computing (DC) Chair: Kazuhiko Iwasaki Vice Chair: Tomohiro Yoneda Secretary: Toshinori Hosokawa, Masato Kitagami =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Toshinori Sueyoshi Vice Chair: Akira Nagoya, Tomomi Sato Secretary: Tetsuo Hironaka, Yuichiro Shibata Assistant: Masahiro Iida =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) DATE: Tue, Nov 28, 2006 09:00 - 17:25 Wed, Nov 29, 2006 13:30 - 17:10 Thu, Nov 30, 2006 09:00 - 16:15 PLACE: TOPICS: Design Gaia 2006 ---A New Frontier in VLSI Design--- ---------------------------------------- Tue, Nov 28 AM CPSY: Computer System (09:00 - 10:40) ---------------------------------------- (1)/CPSY 09:00 - 09:25 A Task Scheduling Method for Reliable Cache Architectures Makoto Sugihara (ISIT), Tohru Ishihara, Kazuaki Murakami (Kyushu Univ.) (2)/CPSY 09:25 - 09:50 A Study on Energy Reduction in Quality-driven Digital Wireless Communication Systems Masayuki Tokunaga (Kyushu Univ), Taizo Tsujimoto (FLEETS), Hiroto Yasuura, Masanori Muroyama (Kyushu Univ) (3)/CPSY 09:50 - 10:15 TBD Soichi Shigeta, Nobuyuki Imamura, Haruyasu Ueda, Hiromichi Kohashi, Miho Murata, Taketoshi Yoshida, Atsushi Kubota, Akira Yasuzato, Yoshimasa Kadooka (Fujitsu Labs. LTD.) (4)/CPSY 10:15 - 10:40 Distributed Network Transaction Appliance using Dynamic Reconfigurable Processor Takashi Isobe (Hitachi, Ltd.) ---------------------------------------- Tue, Nov 28 AM VLD/SLDM: Verification (09:00 - 10:40) ---------------------------------------- (5)/IPSJ-SLDM 09:00 - 09:25 A methodology of generating verification scenarios from specification Ryosuke Oishi, Akio Matsuda, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs. LTD.) (6)/IPSJ-SLDM 09:25 - 09:50 Equivalence Checking using a Decidable Subclass of First-Order-Logic under Equivalence Constraints Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) (7)/IPSJ-SLDM 09:50 - 10:15 Bounded Model Checking for Assertions including Dynamic Local Variables Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) (8)/VLD 10:15 - 10:40 Formal Verification Method for Arithmetic Circuits and Its Evaluation Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech) ---------------------------------------- Tue, Nov 28 AM DC: VLSI Test I (10:55 - 12:10) ---------------------------------------- (9)/DC 10:55 - 11:20 A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure Yudai Kawahara, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (10)/DC 11:20 - 11:45 Test Compression/Decompression with the Decoding Function in Multimedia Cores Yukinori Setohara, Yusuke Nakashima, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (11)/DC 11:45 - 12:10 Test relaxation for N-detection test patterns in broad-side delay testing Kenjiro Taniguchi (Kyushu Inst. of Tech.), Kohei Miyase (JST), Seiji Kajihara, Xiaoqing Wen (Kyushu Inst. of Tech.) ---------------------------------------- Tue, Nov 28 AM VLD/SLDM: Logic and Circuit Design (10:55 - 12:10) ---------------------------------------- (12)/VLD 10:55 - 11:20 Decision Diagram Data Structure to Represent Quantum Circuit Shigeru Yamashita (NAIST), D. Michael Miller (Univ. of Victoria) (13)/IPSJ-SLDM 11:20 - 11:45 Depth-Optimum and Area-Optimal Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) (14)/VLD 11:45 - 12:10 Asymmetric Slope Differential Logic with High-Speed and Low-Power Operation Modes Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki (AIL) ---------------------------------------- Tue, Nov 28 PM DC: VLSI Test II (16:10 - 17:00) ---------------------------------------- (15)/DC 16:10 - 16:35 Test Scheduling for SoCs with Built-In Self-Repairable Memory Cores Yusuke Fukuda, Tomokazu Yoneda, Hideo Fujiwara (NAIST) (16)/DC 16:35 - 17:00 A Self-Test of Dynamically Reconfigurable Processors Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) ---------------------------------------- Tue, Nov 28 PM VLD/SLDM: Behavioral Synthesis/Datapath Synthesis (16:10 - 17:25) ---------------------------------------- (17)/IPSJ-SLDM 16:10 - 16:35 Proposal of a Behavioral Synthesis Method for Asynchronous Circuits in Bundled-data Implementation Naohiro Hamada, Takao Konishi, Hiroshi Saito (The Univ. of Aizu), Tomohiro Yoneda (NII), Takashi Nanya (The Univ. of Tokyo) (18)/VLD 16:35 - 17:00 A Basic Study on Data Path Synthesis Considering Delay Variation Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) (19)/VLD 17:00 - 17:25 Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis Takayuki Obata, Mineo Kaneko (JAIST) ---------------------------------------- Wed, Nov 29 PM (13:30 - 15:10) ---------------------------------------- (20) 13:30 - 14:20 [Special Talk] SystemVerilog Tutorial Kasumi Hamaguchi (Panasonic), Takaaki Akashi (Synopsys), Takeharu Yui (ONW), Kenji Goto (Cadence), Miyuki Okamoto (SANYO), Masashi Sugiura (Zuken), Takehiko Tsuchiya (Toshiba), Yukio Chiwata (Fujitsu), Hirokuni Taketazu (Panasonic), KunDo Lee (Mentor), Yoshio Takamine (Renesas) ----- Break ( 10 min. ) ----- (21) 14:30 - 15:10 [Special Talk] SAT Algorithms and its Applications (tentative) Masahiro Fujita (Univ. of Tokyo) ---------------------------------------- Wed, Nov 29 PM RECONF: Reconfigurable System Application I (15:30 - 17:10) ---------------------------------------- (22)/RECONF 15:30 - 15:55 The development of real time image processing system Kazuo Yamada, Takao Naito (Fuji Xerox) (23)/RECONF 15:55 - 16:20 Real-time Image Processing with FPGA Shoji Sato, Kazuaki Tanaka, Norihiro Abe (KIT) (24)/RECONF 16:20 - 16:45 Real-time Signal Processing for Frequency Modulated Ultrasonic Distance Measurement Takashi Oozasa, Kazuaki Tanaka, Norihiro Abe (KIT) (25)/RECONF 16:45 - 17:10 An Implementation of dynamically reconfigurable multi-rate compatible LDPC decoder Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ---------------------------------------- Wed, Nov 29 PM VLD/SLDM: Performance and Power Enhancement I (15:30 - 17:10) ---------------------------------------- (26)/VLD 15:30 - 15:55 Analysis of Maximum Switching Activities in Sequential Logic Circuits for Power Supply Integrity Validation Hiroyuki Higuchi, Yuzi Kanazawa, Osamu Moriyama (Fujitsu Labs), Noriyuki Ito (Fujitsu) (27)/VLD 15:55 - 16:20 Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech) (28)/VLD 16:20 - 16:45 A fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework Yukihide Kohira (Tokyo Inst. of Tech), Atsushi Takahashi (Tokyo Inst.of Tech) (29)/VLD 16:45 - 17:10 * Toshihiko Yokota (IBM JAPAN) ---------------------------------------- Thu, Nov 30 AM RECONF: Reconfigurable System Application II (09:25 - 10:40) ---------------------------------------- (30)/RECONF 09:25 - 09:50 A Design of AES S-BOX circuit for DPA countermeasure Minoru Sasaki, Keisuke Iwai, Takakazu Kurokawa (NDA.) (31)/RECONF 09:50 - 10:15 Development and evaluation of virus check system using FPGA Yukari Ishida (Toho Univ.), Yosuke Iijima (Univ.of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST) (32)/RECONF 10:15 - 10:40 A template matching circuit using with hwObjects including reconfigurable processing circuits. Rika Sato, Kenji Kudo, Masatoshi Sekine (TUAT) ---------------------------------------- Thu, Nov 30 AM VLD/SLDM: Performance and Power Enhancement II (09:00 - 10:40) ---------------------------------------- (33)/VLD 09:00 - 09:25 On power and delay estimation method for LUT-based FPGAs Ryuji Nakamura, Yusuke Matsunaga (Kyushu Univ.) (34)/VLD 09:25 - 09:50 Architecture Design for Low-Power Multiplier applying Run Time Power Gating Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T) (35)/VLD 09:50 - 10:15 Physical Design for Low-Power Multiplier applying Run time Power Gating Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T.) (36)/VLD 10:15 - 10:40 Design of High Speed Multiplier with Tree-structured partial product adders Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) ---------------------------------------- Thu, Nov 30 AM RECONF: Arithmetic Operation (10:55 - 12:10) ---------------------------------------- (37)/RECONF 10:55 - 11:20 Design of Radix Converters Using Arithmetic Decomposition (2) Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) (38)/RECONF 11:20 - 11:45 Architecture for numerical function generators using EVBDDs Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) (39)/RECONF 11:45 - 12:10 Consideration about Reconfigurable Architecture based on Digit Serial Arithmetics Kazuya Tanigawa, Tetsuo Hironaka (Hirhoshima City Univ.) ---------------------------------------- Thu, Nov 30 AM VLD/SLDM: Physical Design (10:55 - 12:10) ---------------------------------------- (40)/VLD 10:55 - 11:20 Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech) (41)/IPSJ-SLDM 11:20 - 11:45 On Handling Cell Placement with Adjacent Symmetry Constraints for Analog IC Layout Design Shinichi Kouda, Kunihiro Fujiyoshi (TUAT) (42)/VLD 11:45 - 12:10 Waveform measurment of LSI by using on-chip-probe Shinichi Kawagoe, Masayoshi Tachibana (KUT) ---------------------------------------- Thu, Nov 30 PM RECONF: Reconfigurable Architecture I (13:30 - 14:45) ---------------------------------------- (43)/RECONF 13:30 - 13:55 A Low-Power Technique using Resource Sharing Approach for Multi-Context Device Hideaki Monji, Hiroshi Shinohara, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (44)/RECONF 13:55 - 14:20 Area-Efficient Reconfigurable Architecture for Media Processing Kazuma Takahashi, Yukio Mitsuyama, Takao Onoye (Osaka Univ.), Isao Shirakawa (Univ. of Hyogo) (45)/RECONF 14:20 - 14:45 Performance Evaluation of Multi-core DRP for Stream Application Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Hiroki Matsutani, Hideharu Amano (Keio Univ.) ---------------------------------------- Thu, Nov 30 PM VLD/SLDM: System Design Methodology (13:30 - 14:45) ---------------------------------------- (46)/IPSJ-SLDM 13:30 - 13:55 Exploration of Communication Specifications in System Level Design Kazutaka Kobayashi, Ryosuke Yamasaki, Norihiko Yoshida (Saitama Univ.), Shuji Narazaki (Nagasaki Univ.) (47)/VLD 13:55 - 14:20 A Forwarding Unit Optimization Method for Application Processors Toshihiro Hiura, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (48)/IPSJ-SLDM 14:20 - 14:45 Dual Core ASIP for High Speed Image Effect Processing Takahiro Notsu (Osaka Univ.), Tastuhiro Yoshimura (AXELL), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) ---------------------------------------- Thu, Nov 30 PM RECONF: Reconfigurable Architecture II (15:00 - 16:15) ---------------------------------------- (49)/RECONF 15:00 - 15:25 Development of Benchmark Test for comparing Dynamic Reconfigurable Architecture Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU) (50)/RECONF 15:25 - 15:50 An example of function sharing implementation for reconfigurable systems Hideaki Yoshihiro, Takeru Kisanuki, Taiichiro Yatsunami, Yukinobu Kiyota, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto City Univ.) (51)/RECONF 15:50 - 16:15 Delay optimized technology mapping for Variable Grain Logic Cell Hideaki Nakayama, Ryoichi Yamaguchi, Motoki Amagasaki, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) ---------------------------------------- Thu, Nov 30 PM VLD/SLDM: System Design and Development (15:00 - 16:15) ---------------------------------------- (52)/VLD 15:00 - 15:25 Development of A Secure Processor SEP-6 for non-contact type IC card Daisuke Takahashi, Toshimitsu Inomata, Yoshikazu Arai, Masakazu Soga (IPU) (53)/IPSJ-SLDM 15:25 - 15:50 C-Base Design of a Particle Extraction System Kenichi Jyoko, Hirokazu Uetsu, Hirotaka Nakazawa, Takashi Kambe (Kinki Univ) (54)/VLD 15:50 - 16:15 A Hardware Algorithm for the Minimum p-quasi Clique Cover Problem Shuichi Watanabe (The Grad. School, the Univ. of Aizu), Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (The Univ. of Aizu) === Special Interest Group on Computer Architecture (IPSJ-ARC) === === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Jan 17, 2007 - Thu, Jan 18, 2007: Keio Univ. Hiyoshi Campus [Fri, Nov 10], Topics: FPGA and its Application, etc. Wed, Mar 7, 2007 - Fri, Mar 9, 2007: Mielparque Okinawa [Wed, Dec 13], Topics: System-on-silicon design techniques and related VLSs # SECRETARY: Shibuya Toshiyuki(Fujitsu Laboratories) E-mail:  bu       Tel.044-754-2663 # ANNOUNCEMENT: # You will see the latest information at the below WEB page. http://www.ieice.org/~vld/ === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Fri, Dec 15, 2006: Tokyo Univ. Komaba Research Campus [Mon, Oct 16], Topics: Exciting Advanced Computer Systems, etc. Wed, Jan 17, 2007 - Thu, Jan 18, 2007: Keio Univ. Hiyoshi Campus [Fri, Nov 10], Topics: FPGA and its Application, etc. # SECRETARY: Takashi Yokota (Utsunomiya Univ.) TEL +81-28-689-6290, FAX +81-28-689-6290 E-mail:    isu   -u === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Dec 8, 2006: [Tue, Sep 19] Fri, Feb 9, 2007: Kikai-Shinko-Kaikan Bldg [Wed, Dec 20], Topics: VLSI Design and Test, etc # SECRETARY: Masato Kitakami Department of Information and Image Sciences, Faculty of Engineering, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +42.290.3269 E-mail:   f ulty ba-u=== Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Wed, Jan 17, 2007 - Thu, Jan 18, 2007: Keio Univ. Hiyoshi Campus [Fri, Nov 10], Topics: FPGA and its Application, etc. # SECRETARY: Masahiro IIDA (Kumamoto Univ.) E-mail: ii       -uTEL: +81-96-342-3649 FAX: +81-96-342-3649 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Wed, Jan 17, 2007 - Thu, Jan 18, 2007: Keio Univ. Hiyoshi Campus [Fri, Nov 10], Topics: FPGA and its Application, etc. Last modified: 2006-11-24 15:05:49 |
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