|
|
| Chair |
|
Akihisa Yamada (Sharp) |
| Vice Chair |
|
Makoto Ikeda (Univ. of Tokyo) |
| Secretary |
|
Takashi Takenaka (NEC), Shigetoshi Nakatake (Univ. of Kitakyushu) |
|
|
|
| Chair |
|
Hideharu Amano (Keio Univ.) |
| Vice Chair |
|
Akira Asato (Fujitsu), Tsutomu Yoshinaga (Univ. of Electro-Comm.) |
| Secretary |
|
Hidetsugu Irie (Univ. of Electro-Comm.), Koji Nakano (Hiroshima Univ.) |
| Assistant |
|
Hiroaki Inoue (NEC) |
|
|
|
| Chair |
|
Moritoshi Yasunaga (Univ. of Tsukuba) |
| Vice Chair |
|
Shorin Kyo (Renesas), Minoru Watanabe (Shizuoka Univ.) |
| Secretary |
|
Nobuya Watanabe (Okayama Univ.), Yutaka Yamada (Toshiba) |
| Assistant |
|
Yoshiki Yamaguchi (Univ. of Tsukuba) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Michiaki Muraoka (Kochi Univ.) |
| Secretary |
|
Hiroaki Komatsu (Fujitsu), Naoki Iwata (Sony), Nozomu Togawa (Waseda Univ.) |
|
| Conference Date |
Wed, Jan 16, 2013 09:10 - 18:15
Thu, Jan 17, 2013 09:10 - 16:05 |
| Topics |
|
| Conference Place |
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Wed, Jan 16 AM
09:10 - 10:25 |
(1)
RECONF |
09:10-09:35 |
Architecture Evaluation of a Reconfigurable Device MPLD  VLD2012-107 CPSY2012-56 RECONF2012-61 |
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) |
(2)
RECONF |
09:35-10:00 |
A Design Method of Network-on-Chip Architecture for FPGA VLD2012-108 CPSY2012-57 RECONF2012-62 |
Hideki Katabami, Hiroshi Saito (Aizu Univ.) |
(3)
RECONF |
10:00-10:25 |
A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer VLD2012-109 CPSY2012-58 RECONF2012-63 |
Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| |
10:25-10:35 |
Break ( 10 min. ) |
Wed, Jan 16 AM
10:35 - 11:50 |
(4)
RECONF |
10:35-11:00 |
Performance Evaluation of Parametalized Data Compression Hardware for Floating-Point Data Stream VLD2012-110 CPSY2012-59 RECONF2012-64 |
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(5)
RECONF |
11:00-11:25 |
An Architecture for IPv6 Lookup Using Parallel Index Generation Units VLD2012-111 CPSY2012-60 RECONF2012-65 |
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) |
(6)
RECONF |
11:25-11:50 |
Implementation of a neural network for FPGA-based digital DC-DC converters VLD2012-112 CPSY2012-61 RECONF2012-66 |
Yoshihiko Yamabe, Masashi Motomura, Kentaro Yamashita, Hidenori Maruta, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.) |
| |
11:50-13:00 |
Lunch Break ( 70 min. ) |
Wed, Jan 16 PM
13:00 - 14:00 |
(7)
CPSY |
13:00-14:00 |
[Invited Talk]
Challenges and Opportunities for Normally-Off Computing VLD2012-113 CPSY2012-62 RECONF2012-67 |
Hiroshi Nakamura (U. Tokyo) |
| |
14:00-14:10 |
Break ( 10 min. ) |
Wed, Jan 16 PM
14:10 - 15:25 |
(8)
VLD |
14:10-14:35 |
Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number VLD2012-114 CPSY2012-63 RECONF2012-68 |
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) |
(9)
VLD |
14:35-15:00 |
Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic VLD2012-115 CPSY2012-64 RECONF2012-69 |
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
(10)
VLD |
15:00-15:25 |
Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation VLD2012-116 CPSY2012-65 RECONF2012-70 |
Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
| |
15:25-15:35 |
Break ( 10 min. ) |
Wed, Jan 16 PM
15:35 - 16:50 |
(11)
VLD |
15:35-16:00 |
Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers VLD2012-117 CPSY2012-66 RECONF2012-71 |
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(12)
VLD |
16:00-16:25 |
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor VLD2012-118 CPSY2012-67 RECONF2012-72 |
Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) |
(13)
VLD |
16:25-16:50 |
Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu VLD2012-119 CPSY2012-68 RECONF2012-73 |
Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) |
| |
16:50-17:00 |
Break ( 10 min. ) |
Wed, Jan 16 PM
17:00 - 18:15 |
(14)
VLD |
17:00-17:25 |
Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) |
(15)
VLD |
17:25-17:50 |
An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths VLD2012-121 CPSY2012-70 RECONF2012-75 |
Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) |
(16)
VLD |
17:50-18:15 |
The Rohm0.18um Chip Design Trial Using AllianceEDA Tool-set and Cell Library Based on Lambda Rule for Deep-submicron Process
-- Trial of Place and Routing Tools -- VLD2012-122 CPSY2012-71 RECONF2012-76 |
Tatsuya Hosokawa, Naohiko Shimizu (Tokai Univ.) |
Thu, Jan 17 AM
09:10 - 10:25 |
(17)
CPSY |
09:10-09:35 |
An accelerator with minimal data transferring using ring connections VLD2012-123 CPSY2012-72 RECONF2012-77 |
He Guan, Jun Yao, Yasuhiko Nakashima (NAIST) |
(18)
CPSY |
09:35-10:00 |
Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance VLD2012-124 CPSY2012-73 RECONF2012-78 |
Takumi Ishida, Daiki Yamazaki, Masakazu Taniguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) |
(19)
CPSY |
10:00-10:25 |
FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams VLD2012-125 CPSY2012-74 RECONF2012-79 |
Yasin Oge, Masato Yoshimi (Univ. of Electro-Comm.), Takefumi Miyoshi (e-trees), Hideyuki Kawashima (Univ. of Tsukuba), Hidetsugu Irie, Tsutomu Yoshinaga (Univ. of Electro-Comm.) |
| |
10:25-10:35 |
Break ( 10 min. ) |
Thu, Jan 17 AM
10:35 - 11:50 |
(20)
CPSY |
10:35-11:00 |
Low power packet transfer technique on distributed real-time systems VLD2012-126 CPSY2012-75 RECONF2012-80 |
Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) |
(21)
CPSY |
11:00-11:25 |
Comparison between single host multi-GPU system with ExpEther and multi host system VLD2012-127 CPSY2012-76 RECONF2012-81 |
Shimpei Nomura, Tetsuya Nakahama (Keio Univ.), Junichi Higuchi, Yuki Hayashi, Takashi Yoshikawa (NEC), Hideharu Amano (Keio Univ.) |
(22)
CPSY |
11:25-11:50 |
Low latency network topology using multiple links at each host VLD2012-128 CPSY2012-77 RECONF2012-82 |
Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) |
| |
11:50-13:00 |
Lunch Break ( 70 min. ) |
Thu, Jan 17 PM
13:00 - 14:15 |
(23)
RECONF |
13:00-13:25 |
A design of a line buffer module for image proccessing as a library of a high-level synthesis environment VLD2012-129 CPSY2012-78 RECONF2012-83 |
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.) |
(24)
RECONF |
13:25-13:50 |
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs VLD2012-130 CPSY2012-79 RECONF2012-84 |
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) |
(25)
RECONF |
13:50-14:15 |
The method for automation of design verification using UML diagram VLD2012-131 CPSY2012-80 RECONF2012-85 |
Daiki Kano (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Thu, Jan 17 PM
14:25 - 16:05 |
(26)
RECONF |
14:25-14:50 |
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool VLD2012-132 CPSY2012-81 RECONF2012-86 |
Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(27)
RECONF |
14:50-15:15 |
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool VLD2012-133 CPSY2012-82 RECONF2012-87 |
Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(28)
RECONF |
15:15-15:40 |
Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays VLD2012-134 CPSY2012-83 RECONF2012-88 |
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) |
(29)
RECONF |
15:40-16:05 |
Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster VLD2012-135 CPSY2012-84 RECONF2012-89 |
Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Takeshi Takenaka (NEC)
E- :      aj   c
Tel: 044-431-7194 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| CPSY |
Technical Committee on Computer Systems (CPSY) [Latest Schedule]
|
| Contact Address |
Akira ASATO (FUJITSU)
TEL +81-44-754-3233, FAX +81-44-754-3214
E-: a     |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Shorin Kyo (Okayama Univ.)
E-: s  nk wz s
TEL: +81-44-435-5446 |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Nozomu Togawa (Waseda University)
Email sldm2012g     |
| Announcement |
Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/ |
Last modified: 2013-01-11 12:58:42
|