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Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Akira Nagoya (Okayama Univ.)
Vice Chair Tetsuo Hironaka (Hiroshima City Univ.), Shorin Kyo (NEC)
Secretary Tomonori Izumi (Ritsumeikan Univ.), Yohei Hori (Chuo Univ.)
Assistant Nobuya Watanabe (Okayama Univ.)

{INFOMESITEM}
Conference Date Thu, Sep 17, 2009 13:00 - 17:30
Fri, Sep 18, 2009 09:00 - 15:50
Topics Reconfigurable Sysytems, etc. 
Conference Place Yoto Campus, Utsunomiya University 
Address 7-1-2 Yoto, Utsunomiya 321-8585, Japan
Transportation Guide http://www.eng.utsunomiya-u.ac.jp/UFHP/jpn/11access/access.html
Contact
Person
Prof. Takashi Yokota
+81-28-689-6290
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Thu, Sep 17 PM 
13:00 - 14:40
(1) 13:00-13:25 Rea-time detection of rotated patterns using FPGA RECONF2009-19 Yoshifumi Tanida, Tsutomu Maruyama (Tsukuba Univ.)
(2) 13:25-13:50 Component Labeling on the FPGA using Few Logic Elements RECONF2009-20 Yasuaki Ito, Koji Nakano (Hiroshima Univ.)
(3) 13:50-14:15 Performance Evaluation of Levenshtein-Distance Computation on One-Dimensional FPGA Array Cube RECONF2009-21 Masato Yoshimi, Mitsunori Miki (Doshisha Univ.), Yuri Nishikawa, Akihiro Shitara, Hideharu Amano (Keio Univ.), Oskar Mencer (Imperial College London)
(4) 14:15-14:40 FPGA implementation and accuracy evaluation of a power-supply voltage control circuit RECONF2009-22 Masato Soejima, Junya Sakemi, Yuichiro Shibata, Fujio Kurokawa, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ)
  14:40-14:50 Break ( 10 min. )
Thu, Sep 17 PM 
14:50 - 16:30
(5) 14:50-15:15 Low-power oriented clustering and placement tools using routability for FPGAs RECONF2009-23 Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(6) 15:15-15:40 An analysis of frequency in the use LUT logic functions based on P-equivalence class RECONF2009-24 Masaki Shintani, Kota Kato, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(7) 15:40-16:05 Design and Fabrication of Flex Power FPGA with Power Reconfigurability RECONF2009-25 Masakazu Hioki (AIST), Takashi Kawanami (Kanazawa Inst. of Tech.), Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
(8) 16:05-16:30 Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells RECONF2009-26 Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.)
  16:30-16:40 Break ( 10 min. )
Thu, Sep 17 PM 
16:40 - 17:30
(9) 16:40-17:30 [Invited Talk]
YAWARA: A Self-Optimizing Computer System Project RECONF2009-27
Takanobu Baba, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
Fri, Sep 18 AM 
09:00 - 10:15
(10) 09:00-09:25 A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation RECONF2009-28 Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
(11) 09:25-09:50 Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE RECONF2009-29 Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
(12) 09:50-10:15 Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 RECONF2009-30 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ)
  10:15-10:25 Break ( 10 min. )
Fri, Sep 18 AM 
10:25 - 12:05
(13) 10:25-10:50 A Study of Scalable Prototyping System with Small-sized FPGAs RECONF2009-31 Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech)
(14) 10:50-11:15 An FPGA-based Tiny Processing System for Small Embedded System and Education RECONF2009-32 Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto (Hiroshima Univ)
(15) 11:15-11:40 A Study of Topology-adaptive Network-on-Chip for Many-Core SoC RECONF2009-33 Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)
(16) 11:40-12:05 Packet Capturing and Routing Functions on a Network Testbed GtrcNET-10p3 RECONF2009-34 Yuetsu Kodama, Ryousei Takano, Fumihiro Okazaki, Tomohiro Kudoh (AIST)
  12:05-13:10 Lunch ( 65 min. )
Fri, Sep 18 PM 
13:10 - 14:25
(17) 13:10-13:35 High-density Implementation for Reconfigurable Device MPLD RECONF2009-35 Hiroaki Toguchi, Masanori Asaeda, Yutaro Oda, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN CO.LTD)
(18) 13:35-14:00 An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters RECONF2009-36 Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
(19) 14:00-14:25 A writer system not using an imaging lens for 4-context programmable optically reconfigurable gate arrays RECONF2009-37 Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
  14:25-14:35 Break ( 10 min. )
Fri, Sep 18 PM 
14:35 - 15:50
(20) 14:35-15:00 FPGA-based Stream Computation for HPC
-- Designing and Evaluating a Scalable Pipeline-Module for 2D Jacobi Computation --
RECONF2009-38
Kentaro Sano, Yoshiaki Hatsuda, Yasuhiro Otsubo, Satoru Yamamoto (Tohoku Univ.)
(21) 15:00-15:25 A study of an Implementation Method of a Mathematical Function in Reconfigurable Accelerator with High-Precision Floating Point Arithmetic RECONF2009-39 Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
(22) 15:25-15:50 An FPGA-based Architecture for Verifying Collatz Conjecture RECONF2009-40 Yasuaki Ito, Koji Nakano (Hiroshima Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Shorin Kyo (NEC Corporation)
E-: s-kcqc
TEL: 044-431-7543
FAX: 044-431-7589 


Last modified: 2009-09-07 13:23:38


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