Mon, Nov 29 AM
10:40 - 12:00 |
(1)
ICD |
10:40-11:00 |
Evaluation of frequency components of power noise in CMOS digital LSI |
Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) |
(2)
ICD |
11:00-11:20 |
Evaluation of on-chip power noise generation and injection in SRAM core |
Takuya Sawada, Taku Toshikawa, Tsubasa Masui (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) |
(3)
ICD |
11:20-11:40 |
A Consideration of Substrate Noise Sensitivity of Analog Elements |
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) |
(4)
CPM |
11:40-12:00 |
Evaluation of Signal-Integrity Improvement Capability of the Segmental Transmission Line
-- In Its Application to Lines Including Inductances -- |
Hiroki Shimada, Shohei Akita, Masami Ishiguro, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba), Ikuo Yoshihara (Univ. of Miyazaki) |
Mon, Nov 29 PM
13:30 - 14:50 |
| (5) |
13:30-14:10 |
[Invited Talk]
Problems of on-chip interconnection and optical interconnection |
Shin Yokoyama, Yoshiteru Amemiya (Hiroshima Univ.) |
| (6) |
14:10-14:50 |
[Invited Talk]
Present Status and Target Issue of LSI-Chip Optical Interconnection |
Keishi Ohashi (MIRAI-Selete/NEC), Tohru Mogami (MIRAI-Selete) |
| |
14:50-15:00 |
Break ( 10 min. ) |
Mon, Nov 29 PM
15:00 - 16:20 |
| (7) |
15:00-15:40 |
[Invited Talk]
Research Trends and Future Directions for Optical Interconnects Technologies |
Toshiki Sugawara, Yasunobu Matsuoka, Shin-ichi Saito, Naoki Matsushima, Shinji Tsuji (Hitachi) |
| (8) |
15:40-16:20 |
[Invited Talk]
Trend of the ESD design technology of the advanced semiconductor devices |
Hiroyasu Ishizuka (Renesas) |
| |
16:20-16:30 |
Break ( 10 min. ) |
Mon, Nov 29 PM
16:30 - 18:00 |
| (9) |
16:30-18:00 |
Panel Discussion |
Mon, Nov 29 PM
13:30 - 15:10 |
(10)
VLD |
13:30-13:50 |
An Approach to Translate from Mathematical to Electronic Descriptions of Image Processing Algorithm for ITS |
Yukio Fujita, Masanori Tsuzuki, Yoshiya Sugita, Masahiro Fukui (Ritsumeikan Univ.) |
(11)
VLD |
13:50-14:10 |
Rapid SoC Prototyping Based on Virtual Multi-Processor Model |
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) |
(12)
VLD |
14:10-14:30 |
A Scalable Heuristic for Incremental High-Level Synthesis |
Shohei Ono (Univ. Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) |
| (13) |
14:30-14:50 |
|
(14)
DC |
14:50-15:10 |
A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths |
Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| |
15:10-15:25 |
Break ( 15 min. ) |
Mon, Nov 29 PM
15:25 - 17:05 |
(15)
DC |
15:25-15:45 |
Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure |
Hisato Yamaguchi, Makoto Matsuzono, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech./JST) |
(16)
DC |
15:45-16:05 |
A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation |
Yang Shen, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) |
(17)
DC |
16:05-16:25 |
Rotating Test and Pattern Partitioning for Field Test |
Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Insti. Tech.) |
(18)
DC |
16:25-16:45 |
Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders |
Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (19) |
16:45-17:05 |
|
Tue, Nov 30 AM
09:10 - 10:10 |
(20)
ICD |
09:10-09:30 |
17 Gb/s VCSEL Driver Using Double-Pulse Asymmetric Emphasis Technique for Optical Interconnection |
Takaya Taniguchi, Kiichi Yamashita, Kenichi Ohhata (Kagoshima Univ.), Norio Chujo, Toru Yazaki (Hitachi) |
(21)
ICD |
09:30-09:50 |
Improvement and Evaluation of via programmable structured ASIC VPEX |
Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) |
(22)
ICD |
09:50-10:10 |
An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array |
Amarjargal Gundjalam, Minoru Watanabe (Shizuoka Univ.) |
| |
10:10-10:25 |
Break ( 15 min. ) |
Tue, Nov 30 AM
10:25 - 11:45 |
| (23) |
10:25-11:05 |
[Invited Talk]
System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology |
Masahiro Aoyagi (AIST) |
| (24) |
11:05-11:45 |
[Invited Talk]
A wafer-level system integration technology for heterogeneous devices with pseudo-SoC |
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R&D Center) |
Tue, Nov 30 AM
09:30 - 10:30 |
(25)
VLD |
09:30-09:50 |
Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy |
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) |
(26)
VLD |
09:50-10:10 |
Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors |
Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) |
(27)
VLD |
10:10-10:30 |
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes |
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Tue, Nov 30 AM
10:45 - 11:45 |
(28)
VLD |
10:45-11:05 |
FPGA design and test methodology for communication frame processinng |
Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT) |
(29)
VLD |
11:05-11:25 |
Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes |
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) |
| (30) |
11:25-11:45 |
|
Tue, Nov 30 PM
13:15 - 14:35 |
(31)
CPSY |
13:15-13:35 |
A case study of the effective value range analysis for Behavioral synthesis |
Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(32)
CPSY |
13:35-13:55 |
Examination of the virtual wiring for an ASIC emulator using high-speed serial communication |
Toshio Yabuta, Yoshihiro Ichinomiya, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(33)
CPSY |
13:55-14:15 |
A Router Architecture for Priority-Aware On-Chip Networks |
Takuma Kogo, Nobuyuki Yamasaki (Keio Univ) |
(34)
CPSY |
14:15-14:35 |
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU |
Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) |
Tue, Nov 30 PM
13:15 - 14:55 |
(35)
RECONF |
13:15-13:35 |
Circuit Generation using High-Level Synthesis Tool in Reconfigurable HPC System Based on FPGA Arrays |
Kenichi Takahashi, Jiang Li, Hiroki Isogai, Hiroki Banba, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(36)
RECONF |
13:35-13:55 |
OS Functions for a Distributed FPGA Cluster System using Ethernet |
Akira Kojima, Takahiro Kajiyama, Tetsuo Hironaka (Hiroshima City Univ.) |
(37)
RECONF |
13:55-14:15 |
On a Prefetching Heterogeneous MDD Machine |
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) |
(38)
RECONF |
14:15-14:35 |
An FPGA Implementation of CRC Slicing-by-N algorithms |
Amila Akagic, Hideharu Amano (Keio Univ.) |
(39)
RECONF |
14:35-14:55 |
A case study of efficient task scheduling for FPGA-based partially reconfigurable systems |
Yoshiaki Tsutsumi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
Tue, Nov 30 PM
13:15 - 14:15 |
| (40) |
13:15-14:15 |
[Invited Talk]
Paper Writing Guide for International Conferences
-- Implications in VLSI design methodology field -- |
Masanori Hashimoto (Osaka Univ.) |
Tue, Nov 30 PM
14:15 - 14:55 |
(41)
VLD |
14:15-14:35 |
Accurate Delay Analysis Method of Power-Gated Circuit |
Seidai Takeda, Kim Kyundong, Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.) |
| (42) |
14:35-14:55 |
|
Tue, Nov 30 PM
15:30 - 17:00 |
| (43) |
15:30-17:00 |
|
| |
17:00-17:15 |
Break ( 15 min. ) |
Tue, Nov 30 PM
17:15 - 18:15 |
| (44) |
17:15-18:15 |
[Invited Talk]
Photonic-electronic Convergence Technology Based on Silicon
-- Integration of photomic and electric circuits utilizing Siliconphotonics -- |
Seiichi Itabashi, Tai Tsuchizawa, Koji Yamada, Toshifumi Watanabe, Hiroyuki Shinojima, Hidetaka Nishi, Rei Takahashi (NTT Corp.), Kazumi Wada, Yasuhiko Ishikawa (Univ. of Tokyo.) |
Wed, Dec 1 AM
09:30 - 10:30 |
(45)
CPSY |
09:30-09:50 |
A Study of Comparison between In-order and Out-of-order Processor for Many-core Processor Era |
Takefumi Miyoshi, Hidetsugu Irie, Yuuki Matsumura, Tsutomu Yoshinaga (UEC) |
(46)
CPSY |
09:50-10:10 |
Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis |
Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
(47)
CPSY |
10:10-10:30 |
Reliable Digital Signal Transmission Methodology
-- Its Application to the High Speed Bass Line -- |
Shohei Akita, Hiroki Shimada, Masami Ishiguro, Noriyuki Aibe, Moritoshi Yasunaga (Univ. of Tsukuba), Ikuo Yoshihara (Miyazaki Univ.) |
Wed, Dec 1 AM
09:30 - 10:30 |
(48)
RECONF |
09:30-09:50 |
Power-Consumption-Evaluation on the Pattern-Recognition Machine Using Data-Direct-Implementation Approach |
Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba) |
(49)
RECONF |
09:50-10:10 |
Fabrication in Low Power Process and Evaluation of Power Reconfigurable Field Programmable Gate Array |
Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yohei Matsumoto (TUMSAT), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
(50)
RECONF |
10:10-10:30 |
Magnetic Field Measurement for Side-channel Analysis Environment |
Toshihiro Katashita, Yohei Hori, Akashi Satoh (AIST) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Wed, Dec 1 AM
10:45 - 11:45 |
(51)
RECONF |
10:45-11:05 |
An Effective Processing Method for Parallel Loops on FPGA with PCI-Express |
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) |
(52)
RECONF |
11:05-11:25 |
A study of the success rate of MIA under various probability density function estimations |
Yohei Hori (AIST), Takahiro Yoshida (Aoyama Univ.), Toshihiro Katashita, Akashi Satoh (AIST) |
(53)
RECONF |
11:25-11:45 |
Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing |
Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST) |
Wed, Dec 1 AM
09:10 - 10:30 |
(54)
DC |
09:10-09:30 |
SREEP: A Tool for Secure Scan Design Using Shift Register Equivalents |
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.) |
| (55) |
09:30-09:50 |
|
(56)
DC |
09:50-10:10 |
Fault-Injection using Virtualized Environment for Validating Automotive Systems |
Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.) |
(57)
DC |
10:10-10:30 |
Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme |
Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Wed, Dec 1 AM
10:45 - 11:45 |
(58)
VLD |
10:45-11:05 |
ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding |
Mineo Kaneko (JAIST) |
| (59) |
11:05-11:25 |
|
(60)
DC |
11:25-11:45 |
A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description |
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) |
Wed, Dec 1 PM
13:15 - 13:55 |
(61)
RECONF |
13:15-13:55 |
[Invited Talk]
Monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS |
Tatasuya Naito, Tatsuya Ishida (Toshiba), Takeshi Onoduka (Covalent Materials), Masahito Nishigoori, Takeo Nakayama, Yoshihiro Ueno, Yasumi Ishimoto, Akihiro Suzuki, Chung Weicheng (Toshiba), Raminda Madurawe (readyASIC), Sheldon Wu (China International Intellectual Property Services), Shu Ikeda (tei Solutions), Hisato Oyamatsu (Toshiba) |
| |
13:55-14:10 |
Break ( 15 min. ) |
Wed, Dec 1 PM
14:10 - 14:50 |
(62)
RECONF |
14:10-14:30 |
An FPGA Implementation of Face Detection Recognition System for automobile using Impulse C |
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.) |
(63)
RECONF |
14:30-14:50 |
FPGA Accelaration Default Intensity Model |
Takaaki Yokoyama, Hideharu Amano (Keio Univ.) |
Wed, Dec 1 PM
13:15 - 14:35 |
(64)
VLD |
13:15-13:35 |
Adjacent Insertion and Its Effectiveness in Code-Based 3-D Placement |
Shin Uesugi, Mineo Kaneko (JAIST) |
(65)
VLD |
13:35-13:55 |
On pruning rules in exact algorithms for the minimum rectilinear Steiner arborescence problem |
Masayuki Nagase, Toshihiko Takahashi (Niigat Univ.) |
(66)
VLD |
13:55-14:15 |
Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications |
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(67)
VLD |
14:15-14:35 |
Develop A Clock Tree Generator into Open-source CAD System. |
Takuya Higuchi, Jun'ichiro Ogane, Naohiko Shimizu (Tokai Univ.) |
| |
14:35-14:50 |
Break ( 15 min. ) |
Wed, Dec 1 PM
14:50 - 15:50 |
(68)
VLD |
14:50-15:10 |
Optimal adder architecture in ultra low voltage domain |
Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) |
(69)
VLD |
15:10-15:30 |
A proposal for VLSI model for evaluation of rush current by power gating |
Hiroto Yamaguchi, Junki Miyajima, Tomohiko Sumi, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) |
(70)
VLD |
15:30-15:50 |
Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control |
Xin Man (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Tomoo Kimura, Koji Kai (Panasonic), Shinji Kimura (Waseda Univ.) |
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