|
|
| Chair |
|
Akira Onozawa (NTT) |
| Vice Chair |
|
Kimiyoshi Usami (Shibaura Inst. of Tech.) |
| Secretary |
|
Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
|
| Conference Date |
Mon, Sep 27, 2010 14:00 - 17:30
Tue, Sep 28, 2010 10:00 - 16:15 |
| Topics |
Physical design, etc |
| Conference Place |
Kyoto Institute of Technology |
| Address |
Matsugasakihashigami-cho, Sakyou-ku, Kyoto 606-8585 Japan |
| Transportation Guide |
Take the “Kokusai Kaikan” bound Karasuma Line Subway to “Matsugasaki” Station, and walk east for about 8 min.
http://www.kit.ac.jp/01/01_110000.html |
Contact
Person |
Prof. Kazutoshi Kobayashi
+81-75-724-7452 |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Mon, Sep 27 PM
14:00 - 15:15 |
| (1) |
14:00-14:25 |
Ordered Coloring for Skew Adjustability-Aware Resource Binding  VLD2010-42 |
Mineo Kaneko (JAIST) |
| (2) |
14:25-14:50 |
Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors VLD2010-43 |
Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) |
| (3) |
14:50-15:15 |
Design and Evaluation of Arbiter Physical Unclonable Functions VLD2010-44 |
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino (Ritsumeikan Univ.) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Mon, Sep 27 PM
15:30 - 17:30 |
| (4) |
15:30-16:30 |
[Invited Talk]
Analog Circuit Optimization Using Pareto-Optimality VLD2010-45 |
Yu Liu, Masato Yoshioka, Katsumi Homma, Yuzi Kanazawa (Fujitsu Labs), Toshiyuki Shibuya (Fujitsu Labs of America) |
| (5) |
16:30-17:00 |
[Invited Talk]
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit VLD2010-46 |
Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) |
| (6) |
17:00-17:30 |
[Invited Talk]
Length Matching Routing on Single Layer for PCB Routing Design VLD2010-47 |
Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) |
Tue, Sep 28 AM
10:00 - 11:40 |
| (7) |
10:00-10:25 |
A Method of Analog IC Placement with Common Centroid Constraints VLD2010-48 |
Keitaro Ue, Kunihiro Fujiyoshi (TUAT) |
| (8) |
10:25-10:50 |
Analog Layout Retargeting with Constraint Extraction by Matching of Fundamental Circuit Components and Layout Regularity VLD2010-49 |
Kazuhiko Shibata, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| (9) |
10:50-11:15 |
Regularity-Oriented Compaction with Z-cut Perturbation VLD2010-50 |
Shigetoshi Nakatake (Univ. of Kitakyushu) |
| (10) |
11:15-11:40 |
Fast Optimization on Minimum Perturbation Placement Realization VLD2010-51 |
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) |
| |
11:40-13:20 |
Break ( 100 min. ) |
Tue, Sep 28 PM
13:20 - 14:20 |
| (11) |
13:20-14:20 |
[Invited Talk]
Application of Ultra Low-power Circuit Techniques to Wireless Terminals in Wide Area Ubiquitous Network
-- Approach to Nano-watt Wireless Sensor Nodes -- VLD2010-52 |
Yuichi Kado (Kyoto Inst. of Tech.), Mitsuru Harada, Mamoru Ugajin, Akihiro Yamagishi, Mitsuo Nakamura (NTT) |
| |
14:20-14:35 |
Break ( 15 min. ) |
Tue, Sep 28 PM
14:35 - 16:15 |
| (12) |
14:35-15:00 |
A study of temperature characteristics of ring-oscillator based threshold voltage estimation VLD2010-53 |
Takumi Uezono, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
| (13) |
15:00-15:25 |
Analysis and Evaluation of Simultaneous Switching Noise of FPGA VLD2010-54 |
Yo Takahashi, Toshio Sudo (SIT), Kunio Ota, Kazuhisa Matsuge (Toshiba) |
| (14) |
15:25-15:50 |
Measurement Circuits for Acquiring SET PulseWidth Distribution with Fine Time Resolution VLD2010-55 |
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| (15) |
15:50-16:15 |
Modeling of Latching Probability of Soft-Error-Induced Pulse VLD2010-56 |
Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Akihisa Yamada (Sharp)
E- :     a    s rp
Tel: +81-743-65-2531, Fax: +81-743-65-0554 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
Last modified: 2010-09-17 12:43:03
|