IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

===============================================
Technical Committee on Hardware Security (HWS)
Chair: Tsutomu Matsumoto (Yokohama National Univ.) Vice Chair: Shinichi Kawamura (Toshiba), Makoto Ikeda (Univ. of Tokyo)
Secretary: Noriyuki Miura (Kobe Univ.), Hiroki Kunii (SECOM)

===============================================
Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Hideto Hidaka (Renesas) Vice Chair: Makoto Nagata (Kobe Univ.)
Secretary: Takashi Hashimoto (Panasonic), Masanori Natsui (Tohoku Univ.)
Assistant: Hiroyuki Ito (Tokyo Inst. of Tech.), Masatoshi Tsuge (Socionext), Tetsuya Hirose (Kobe Univ.)

DATE:
Mon, Oct 29, 2018 13:00 - 17:15

PLACE:


TOPICS:
HardwareSecurity, etc.

----------------------------------------
Mon, Oct 29 PM (13:00 - 14:15)
----------------------------------------

(1) 13:00 - 13:25
Study on Signal-to-Noise Ratio Simulation of Side-Channel Traces Leaked from AES Circuit using EDA tool
Toshiaki Teshima, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.)

(2) 13:25 - 13:50
Countermeasures for power noise and side-channel leakage in crypto fmodules (I)
Kazuki Monta, Sousuke Sato, Akihiro Tsukioka (Kobe Univ.), Takaaki Okidono (ECSEC), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)

(3) 13:50 - 14:15
Hardware Design of High Precision Discrete Gaussian Sampler for Lattice-based Cryptography
Keitaro Koga (UTokyo), Awano Hiromitsu (VDEC), Ikeda Makoto (UTokyo)

----------------------------------------
Mon, Oct 29 PM (14:30 - 15:45)
----------------------------------------

(4) 14:30 - 14:55
An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU)

(5) 14:55 - 15:20
Selection and evaluation of optimal bases in the case of implementing Q-RNS MR algorithm in FPGA
Yoshihiro Kori, Daisuke Fujimoto, Yu-ichi Hayasi (NAIST), Naofumi Homma (Tohoku Univ.)

(6) 15:20 - 15:45
A Design and Implementation of Ring-LWE Cryptography Hardware Based on Number Theoretic Transform
Sora Endo, Rei Ueno, Takafumi Aoki, Naofumi Homma (Tohoku Univ.)

----------------------------------------
Mon, Oct 29 PM (16:00 - 17:15)
----------------------------------------

(7) 16:00 - 16:25
Evaluation of Availability on Cache Leakage from OSS-RSA
Hayato Mori, Rei Ueno (Tohoku Univ.), Junko Takahashi (NTT), Yuichi Hayashi (naist), Naohumi Honma (Tohoku Univ.)

(8) 16:25 - 16:50
Impact of Instruction Replacing Laser Fault Attack on Implementation of Pairing Computation on ARM Processor
Junichi Sakamoto, Tsutomu Matsumoto (YNU)

(9) 16:50 - 17:15
Security Evaluations of Automotive Attacks on FlexRay
Junko Takahashi, Masashi Tanaka (NTT)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

# CONFERENCE SPONSORS:
- This conference is co-sponsored by IEEE SSCS Japan Chapter, IEEE SSCS Kansai Chapter, Kobe University Gratuate School of Science, Technology, and Innovation.


=== Technical Committee on Hardware Security (HWS) ===
# FUTURE SCHEDULE:

Thu, Dec 13, 2018: Tokyo Univ. Takeda Bldg. Takeda Hall [Fri, Nov 30], Topics: Hardware Security Forum 2018

# SECRETARY:
Noriyuki Miura(Kobe University), Hiroki Kunii(SECOM)
E-mail:hws-c

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Wed, Dec 5, 2018 - Fri, Dec 7, 2018: Satellite Campus Hiroshima [Mon, Oct 8], Topics: Design Gaia 2018 -New Field of VLSI Design-
Fri, Dec 21, 2018 - Sun, Dec 23, 2018: [Fri, Oct 12]
Mon, Jan 28, 2019 - Tue, Jan 29, 2019:

# SECRETARY:
Takashi Hashimoto (Panasonic Corporation)
E-mail: 1967pac


Last modified: 2018-10-18 11:43:29


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to HWS Schedule Page]   /   [Return to ICD Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan