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Technical Committee on VLSI Design Technologies (VLD)
Chair: Yusuke Matsunaga (Kyushu Univ.) Vice Chair: Takashi Takenana (NEC)
Secretary: Hiroyuki Tomiyama (Ritsumeikan Univ.), Daisuke Fukuda (Fujitsu Labs.)
Assistant: Ittetsu Taniguchi (Ritsumeikan Univ.)

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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Masahiro Fukui (Ritsumeikan Univ.)
Secretary: Masao Yokoyama (Sharp), Yasuhiro Takashima (Kitakyushu City Univ.), Takeo Nishide (Toshiba)

DATE:
Wed, May 11, 2016 10:00 - 17:00

PLACE:


TOPICS:
System Design, etc.

----------------------------------------
Wed, May 11 AM (10:00 - 11:40)
----------------------------------------

(1)/VLD 10:00 - 10:25
An Application of Subgradient Method to Delay Analysis
Hiroshi Miyashita, Koutaro Kawaraguchi (The Univ. of Kitakyushu)

(2)/VLD 10:25 - 10:50
Self-Aligned Double Patterning-Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT)

(3) 10:50 - 11:15


(4) 11:15 - 11:40


----- Lunch Break ( 80 min. ) -----

----------------------------------------
Wed, May 11 PM (13:00 - 14:15)
----------------------------------------

(5) 13:00 - 13:25


(6) 13:25 - 13:50


(7)/VLD 13:50 - 14:15
Multi bit soft error tolerant FPGA architecture
Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

----- Break ( 15 min. ) -----

----------------------------------------
Wed, May 11 PM (14:30 - 15:45)
----------------------------------------

(8)/VLD 14:30 - 14:55
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

(9)/VLD 14:55 - 15:20
A Note on Scheduling Problem Considering the Radiation Resistance of Registers
Keisuke Inoue (KTC), Mineo Kaneko (JAIST)

(10)/VLD 15:20 - 15:45
MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA
Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.)

----- Break ( 15 min. ) -----

----------------------------------------
Wed, May 11 PM (16:00 - 17:00)
----------------------------------------

(11)/VLD 16:00 - 17:00
[Invited Talk]
Challenges of DA Technologies for the Future
-- For the Establishment of Next Generation DA Technologies --
Michiaki Muraoka (Kochi Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Mon, May 16, 2016 - Tue, May 17, 2016: Institute of Industrial Science, University of Tokyo [unfixed], Topics: LSI and System Workshop 2016
Thu, Jun 16, 2016 - Fri, Jun 17, 2016: Hirosaki Shiritsu Kanko-kan [Fri, Apr 15], Topics: System, signal processing and related topics

# SECRETARY:
Hiroyuki Tomiyama (Ritsumeikan University)
E-mail: htfci
Phone: 077-561-4928

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:

Mon, May 16, 2016 - Tue, May 17, 2016: Institute of Industrial Science, University of Tokyo [unfixed], Topics: LSI and System Workshop 2016

# SECRETARY:
Yasuhiro Takashima (University of Kitakyushu)
Email sldm2015isenvk-u

# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2016-04-06 08:17:25


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