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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kazutoshi Wakabayashi (NEC)
Vice Chair Atsushi Takahashi (Tokyo Inst. of Tech.)
Secretary Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.)

Conference Date Wed, Mar 11, 2009 10:30 - 17:55
Thu, Mar 12, 2009 09:15 - 17:55
Fri, Mar 13, 2009 09:15 - 16:05
Topics Design Technology for a System-on-Silicon 
Conference Place  

Wed, Mar 11 AM 
10:30 - 11:45
(1) 10:30-10:55 Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.)
(2) 10:55-11:20 Random Testing for Arithmetic Optimization of C compilers Hironobu Awazu, Nagisa Ishiura (Kwansei Gakuin Univ.)
(3) 11:20-11:45 Execution Trace Mining for Intratask DVFS in Embedded Systems Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
  11:45-13:00 Lunch ( 75 min. )
Wed, Mar 11 PM 
13:00 - 13:50
(4) 13:00-13:50 [Invited Talk]
Model-Based Development for automotive control systems
-- Modeling Technique of microcontroller --
Yasuo Sugure, Shigeru Oho (Hitachi Ltd.)
  13:50-14:00 Break ( 10 min. )
Wed, Mar 11 PM 
14:00 - 15:40
(5) 14:00-14:25 Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
(6) 14:25-14:50 Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints Sho Kodama, Yusuke Matsunaga (Kyushu Univ.)
(7) 14:50-15:15 Fault Tolerant Datapath Synthesis Starting with Triple Algorithm Redundancy Yutaka Tsuboishi, Mineo Kaneko (JAIST)
(8) 15:15-15:40 On the Minimization of Input Variables for Incompletely Specified Index Generation Functions Takaaki Nakamura, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
  15:40-15:50 Break ( 10 min. )
Wed, Mar 11 PM 
15:50 - 17:55
(9) 15:50-16:15 A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
(10) 16:15-16:40 A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
(11) 16:40-17:05 A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
(12) 17:05-17:30 Fast Optimization on Minimum Perturbation Placement Realization Yuki Kouno, Yasuhiro Takashima (The Univ. of Kitakyushu), Atsushi Takahashi (Tokyo Inst. of Tech.)
(13) 17:30-17:55 Delay Estimation of Sub-path under Path-delay Test Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.)
Thu, Mar 12 AM 
09:15 - 10:55
(14) 09:15-09:40 Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(15) 09:40-10:05 The implementation of DES cryptographic circuit and the evaluation of DPA attack resistance using Domino-RSL technique Kenji Kojima, Kazuki Okuyama, Yuki Makino, Takeshi Fujino (Ritsumeikandai Univ.)
(16) 10:05-10:30 Differential Power Analysis of bit-value against cipher implementation on FPGA Kazuki Okuyama, Kenji Kojima, Yuki Makino, Takeshi Fujino (Ritsumei Univ.)
(17) 10:30-10:55 A Formal Verification Method for On-Chip Programmable Interconnect Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
  10:55-11:05 Break ( 10 min. )
Thu, Mar 12 AM 
11:05 - 11:55
(18) 11:05-11:30 High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT)
(19) 11:30-11:55 A memory-reduction method for multi-rate LDPC encoder Wenming Tang, Xianghui WEI, Satoshi Goto (Waseda Univ.)
  11:55-13:00 Lunch ( 65 min. )
Thu, Mar 12 PM 
13:00 - 14:40
(20) 13:00-13:25 Emulation of Sequential Circuits by a Parallel Branching Program Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.)
(21) 13:25-13:50 A Proposal of an Adaptive Network on Chip for Multi-Core SoC Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ)
(22) 13:50-14:15 A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST)
(23) 14:15-14:40 Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST)
  14:40-14:50 Break ( 10 min. )
Thu, Mar 12 PM 
14:50 - 16:30
(24) 14:50-15:15 A ring segmented bus architrcture for Globally Asynchronous Locally Synchronous System Masafumi Kondo, Yoichiro Sato (Okayama Prefectural Univ), Kazuyuki Tashiro (FUJITSU TEN), Tomoyuki Yokogawa, Michiyoshi Hayase (Okayama Prefectural Univ)
(25) 15:15-15:40 Formal verification of GALS system designs using UPPAAL Kazuaki Kirita, Tomoyuki Yokogawa, Hisashi Miyazaki, Yoichiro Sato, Michiyoshi Hayase (Okayama Pref. Univ.)
(26) 15:40-16:05 A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(27) 16:05-16:30 Delay Reduction Algorithm by Balancing Distribution of Traffic for Odd-Even Turn Model in NoCs Shingo Wakita, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
  16:30-16:40 Break ( 10 min. )
Thu, Mar 12 PM 
16:40 - 17:55
(28) 16:40-17:05 Low Power Deblocking Filter Implementation Method for H.264/AVC Yoshinori Hayashi, Tomohiro Akita, Tian Song, Takashi Shimamoto (Tokushima Univ.)
(29) 17:05-17:30 Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC Hiroki Kuniyasu, Tomoyuki Kishida, Tian Song, Takashi Shimamoto (Tokushima Univ.)
(30) 17:30-17:55 Asynchronous $\pm2^k$ Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.)
Fri, Mar 13 AM 
09:15 - 10:30
(31) 09:15-09:40 An algorithm for building RTL library Masato Kawai, Hirofumi Kawauchi, Toshio Morikawa, Masaaki Ohtsuki, Masahiro Fukui (Ritsumeikan Univ.)
(32) 09:40-10:05 A Battery Charge/Discharge Simulator Close to Actual Behavior Sayaka Iwakoshi, Keita Kojima, Kazunori Toi, Masahiro Fukui (Ritsumeikan Univ.)
(33) 10:05-10:30 A Study for Power Grid Simulator by using GPU Hisako Sugano, Shinichi Nishizawa, Taiki Hashizume, Masahiro Fukui (Ritsumeikan Univ.)
  10:30-10:40 Break ( 10 min. )
Fri, Mar 13 AM 
10:40 - 11:55
(34) 10:40-11:05 Layout Aware Cell Clustering for Body Biasing Koichi Hamamoto (Osaka Univ.), Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST)
(35) 11:05-11:30 Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST)
(36) 11:30-11:55 Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. of Tech.)
  11:55-13:00 Lunch ( 65 min. )
Fri, Mar 13 PM 
13:00 - 14:40
(37) 13:00-13:25 Implementation and performance measurement of low-power multiplier applying Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai (Shibaura Inst. of Tech.), Seidai Takeda (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.)
(38) 13:25-13:50 Physical design and Evaluation of On-chip Leakage Monitor at 65nm devices Satoshi Koyama, Kimiyoshi Usami (Shibaura Inst. of Tech.)
(39) 13:50-14:15 Performance Evaluations of nMOS Level Shifter Circuits Makoto Otsu, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo), Shuji Nishi, Tomoyuki Nagai, Yasushi Kubota (Sharp Corp.)
(40) 14:15-14:40 Performance Evaluations of Two Measures for Statistical Design Yuki Yoshida, Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.)
  14:40-14:50 Break ( 10 min. )
Fri, Mar 13 PM 
14:50 - 16:05
(41) 14:50-15:15 Study of high-speed low-power system LSI for sub-threshold operation Makoto Tsurukubo, Shigeyoshi Watanabe (Shonan Inst. of Tech Graduate school)
(42) 15:15-15:40 Reduced pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
(43) 15:40-16:05 Examination of Low-power system LSI architecture by scheduling algorithm Yoshikazu Sato, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Ichiro Kohno (Renesas Technology Corp.)
E-: his
TEL: +81-42-312-5873 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/


Last modified: 2009-02-18 17:26:08


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