Thu, Jul 30 AM
11:00 - 12:30 |
(1)
CPSY |
11:00-11:30 |
Instruction Prefetcher focusing on properties of Prefetch Distance |
Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo) |
| (2) |
11:30-12:00 |
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| (3) |
12:00-12:30 |
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12:30-13:30 |
Break ( 60 min. ) |
Thu, Jul 30 PM
13:30 - 15:00 |
| (4) |
13:30-14:00 |
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| (5) |
14:00-14:30 |
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(6)
CPSY |
14:30-15:00 |
Distributed Runtime Environment with Julia Language |
Hidemoto Nakada (AIST) |
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15:00-15:15 |
Break ( 15 min. ) |
Thu, Jul 30 PM
15:15 - 16:45 |
(7)
CPSY |
15:15-15:45 |
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(8)
CPSY |
15:45-16:15 |
Automated Fixed-Point Bit-Length Optimization for OS-ELM |
Mineto Tsukada, Hiroki Matsutani (Keio Univ.) |
(9)
CPSY |
16:15-16:45 |
Preliminary examination of normally-off power management for local 5G base station |
Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura (UTokyo) |
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16:45-17:00 |
Break ( 15 min. ) |
Thu, Jul 30 PM
17:00 - 18:00 |
(10)
CPSY |
17:00-17:30 |
Proposal for an IP-based Design Environment for CGRA Applications |
Ayaka Ohwada, Takuya Kojima, Hideharu Amano (Keio Univ.) |
(11)
CPSY |
17:30-18:00 |
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Takuya Kojima, Ayaka Ohwada, Hideharu Amano (Keio Univ.) |
Fri, Jul 31 AM
09:15 - 10:45 |
| (12) |
09:15-09:45 |
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(13)
CPSY |
09:45-10:15 |
A Case for Acceleration of 2D Graph-Based SLAM using FPGA |
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
| (14) |
10:15-10:45 |
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10:45-11:00 |
Break ( 15 min. ) |
Fri, Jul 31 AM
11:00 - 12:30 |
(15)
CPSY |
11:00-11:30 |
The next generation FiC with M-KUBOS board |
Hideharu Amano, Kazuei Hironaka, Kensuke Iizuka (Keio Univ.) |
(16)
CPSY |
11:30-12:00 |
Task Offloading of a Distributed and Cooperative Cache Server using FPGA |
Teppei Yamagishi (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) |
(17)
CPSY |
12:00-12:30 |
A study of an FPGA-based cluster computing with high-speed serial links |
Fan Ruochong, Ao Yun, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba) |
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12:30-15:15 |
Break ( 165 min. ) |
Fri, Jul 31 PM
15:15 - 16:45 |
| (18) |
15:15-15:45 |
(cancelled) |
(19)
DC |
15:45-16:15 |
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns |
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) |
(20)
DC |
16:15-16:45 |
A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount |
Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) |
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16:45-17:00 |
Break ( 15 min. ) |
Fri, Jul 31 PM
17:00 - 18:30 |
(21)
DC |
17:00-17:30 |
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Daichi Minamide, Tatsuhiro Tsuchiya (Osaka Univ.) |
(22)
DC |
17:30-18:00 |
An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation |
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
(23)
DC |
18:00-18:30 |
A Study on Error Correction Coding For Matrix Multiplications Based On Product Codes |
Yuki Katsu, Haruhiko Kaneko (Titech) |
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