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Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Tetsuo Hironaka (Hiroshima City Univ.)
Vice Chair Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.)
Secretary Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant Kazuya Tanikagawa (Hiroshima City Univ.)

Conference Date Thu, Sep 18, 2014 13:00 - 18:10
Fri, Sep 19, 2014 09:00 - 15:05
Topics Reconfigurable Systems, etc. 
Conference Place  
Transportation Guide JR山陽本線宮島口駅下車、宮島口桟橋から船で10分、宮島桟橋下船徒歩25分
Contact
Person
Hiroshima City Univ., Kazuya Tanikagawa

Thu, Sep 18 PM  Invited talk (1)
13:00 - 13:50
(1) 13:00-13:50 [Invited Talk]
Architecture Development for the Real-time Computer-Aided Diagnosis of Colorectal Endoscopic Images with NBI Magnification
Tetsushi Koide (Hiroshima Univ.)
  13:50-14:10 Break ( 20 min. )
Thu, Sep 18 PM  Fault-tolerant FPGA
14:10 - 15:25
(2) 14:10-14:35 Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(3) 14:35-15:00 A study of run-time fault detection mechanism for fault-tolerant FPGAs Kentaro Fujisawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(4) 15:00-15:25 Radiation tolerance of a holographic memory part on an optically reconfigurable gate array Retsu Moriwaki, Hiroyuki Ito (Shizuoka Univ.), Akira Maekawa (Kobe City College of Tech.), Minoru Watanabe (Shizuoka Univ.), Akifumi Ogiwara (Kobe City College of Tech.)
  15:25-15:45 Break ( 20 min. )
Thu, Sep 18 PM  Network on Chip and communication systems related to FPGA
15:45 - 17:00
(5) 15:45-16:10 Challenge for Ultrafast 10K-Node NoC emulation on FPGA Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.)
(6) 16:10-16:35 Dynamically reconfigurable protocol-processing hardware for communications SoC Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu (NTT)
(7) 16:35-17:00 A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies Masato Inagi (Hiroshima City Univ.), Yuichi Nakamura (NEC), Yasuhiro Takashima (Univ. of Kitakyusyu), Shin'ichi Wakabayashi (Hiroshima City Univ.)
  17:00-17:20 Break ( 20 min. )
Thu, Sep 18 PM  Device architecture
17:20 - 18:10
(8) 17:20-17:45 On The Second Flex Power FPGA Chip with SOTB Transistors Hanpei Koike (AIST), Chao Ma (Meiji Univ.), Masakazu Hioki, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST)
(9) 17:45-18:10 Parallel-operation-oriented optically reconfigurable gate array Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
Fri, Sep 19 AM  Invited Talk (2)
09:00 - 09:50
(10) 09:00-09:50 [Invited Talk]
Research & Development of FPGA Applications in A Company
Takefumi Miyoshi (e-trees.Japan)
  09:50-10:10 Break ( 20 min. )
Fri, Sep 19 AM  Numerical computation and pipeline design
10:10 - 11:25
(1) 10:10-10:35 Building a Mixed Software Hardware Pipeline on CPU-FPGA Platforms Takaaki Miyajima (Keio Univ.), David Thomas (ICL), Hideharu Amano (Keio Univ.)
(2) 10:35-11:00 Evaluation and Implementation of the Calculation Feature to PEACH2 Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Univ. of Tokyo), Hideharu Amano (Keio Univ.)
(3) 11:00-11:25 GRAPE9-MPX: A development of an accelerator dedicated for arbitrary-precision arithmetic by the FPGA boards Shinji Motoki (KEK), Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Toshiyuki Fukushige, Atsushi Kawai (K & F Computing Research), Junichiro Makino (RIKEN/TITECH)
  11:25-13:05 Break ( 100 min. )
Fri, Sep 19 AM  FPGA application
13:05 - 13:55
(4) 13:05-13:30 Discussion for speed up of three-dimensional space imaging using sound waves Keiko Oda, Akira Kojima, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
(5) 13:30-13:55 FPGA implementation of a Compact Processor Yukiyama for tiny SoC Yuichi Watanabe, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
  13:55-14:15 Break ( 20 min. )
Fri, Sep 19 PM 
14:15 - 15:05
(6) 14:15-14:40 A Trial Hardware Design of a Recursive Function to Solve "OX game" by Code-Modification and High-Level Synthesis Masashi Ohno, Yu Nakahara, Tomonori Izumi, Lin Meng (Ritsumeikan Univ.)
(7) 14:40-15:05 Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  


Last modified: 2014-09-05 12:13:31


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