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Technical Committee on VLSI Design Technologies (VLD)
Chair: Takashi Takenana (NEC) Vice Chair: Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary: Daisuke Fukuda (Fujitsu Labs.), Shinobu Nagayama (Hiroshima City Univ.)
Assistant: Parizy Matthieu (Fujitsu Labs.)

===============================================
Technical Committee on Component Parts and Materials (CPM)
Chair: Satoru Noge (Numazu National College of Tech.) Vice Chair: Fumihiko Hirose (Yamagata Univ.)
Secretary: Junichi Kodate (NTT), Nobuyuki Iwata (Nihon Univ.)
Assistant: Takashi Sakamoto (NTT), Yuichi Nakamura (Toyohashi Univ. of Tech.)

===============================================
Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Minoru Fujishima (Hiroshima Univ.) Vice Chair: Hideto Hidaka (Renesas)
Secretary: Takeshi Yoshida (Hiroshima Univ.), Makoto Takamiya (Univ. of Tokyo)
Assistant: Takashi Hashimoto (Panasonic), Masanori Natsui (Tohoku Univ.), Hiroyuki Ito (Tokyo Inst. of Tech.), Pham Konkuha (Univ. of Electro-Comm.)

===============================================
Technical Committee on Image Engineering (IE)
Chair: Seishi Takamura (NTT)
Vice Chair: Takayuki Hamamoto (Tokyo Univ. of Science), Atsuro Ichigaya (NHK)
Secretary: Yukihiro Bandoh (NTT), Takamichi Miyata (Chiba Inst. of Tech.)
Assistant: Kei Kawamura (KDDI R&D Labs.), Keita Takahashi (Nagoya Univ.)

===============================================
Technical Committee on Computer Systems (CPSY)
Chair: Yasuhiko Nakashima (NAIST)
Vice Chair: Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Tokyo)
Secretary: Takashi Miyoshi (Fujitsu Labs.), Michihiro Koibuchi (NII)
Assistant: Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (NAIST)

===============================================
Technical Committee on Dependable Computing (DC)
Chair: Michiko Inoue (NAIST) Vice Chair: Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Secretary: Masayoshi Yoshimura (Kyoto Sangyo Univ.), Haruhiko Kaneko (Tokyo Inst. of Tech.)

===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Minoru Watanabe (Shizuoka Univ.)
Vice Chair: Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.)
Secretary: Yoshiki Yamaguchi (Univ. of Tsukuba), Kazuya Tanigawa (Hiroshima City Univ.)
Assistant: Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)

===============================================
Special Interest Group on System Architecture (IPSJ-ARC)
Chair: Masahiro Goshima
Secretary: Takatsugu Ono, Masaaki Kondo, Yohei Hasegawa, Shinobu Miwa

===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Kiyoharu Hamaguchi
Secretary: Takeo Nishide (Toshiba), Yasuhiro Takashima (Kitakyushu City Univ.)

DATE:
Mon, Nov 28, 2016 10:30 - 17:40
Tue, Nov 29, 2016 09:00 - 17:45
Wed, Nov 30, 2016 09:00 - 15:00

PLACE:
(http://www.ritsumei.ac.jp/accessmap/oic/. Prof. Ittetsu Taniguchi. +81-72-665-2500)

TOPICS:
Design Gaia 2016 -New Field of VLSI Design-

----------------------------------------
Mon, Nov 28 AM (10:30 - 11:20)
----------------------------------------

(1)/VLD 10:30 - 10:55
A Design Method of Circuits to Generate Stochastic Numbers with the Minimum Inputs
Ritsuko Muguruma, Shigeru Yamashita (Ritsmeikan Univ.)

(2)/VLD 10:55 - 11:20
Scheduling of Malleable Fork-Join Tasks
Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)

----------------------------------------
Mon, Nov 28 AM (10:30 - 11:45)
----------------------------------------

(3) 10:30 - 10:55


(4) 10:55 - 11:20


(5) 11:20 - 11:45


----- Lunch Break ( 60 min. ) -----

----------------------------------------
Mon, Nov 28 PM (12:45 - 14:00)
----------------------------------------

(6)/VLD 12:45 - 13:10
2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting
Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.)

(7)/VLD 13:10 - 13:35
Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)
Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech)

(8)/VLD 13:35 - 14:00
Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA
Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)

----------------------------------------
Mon, Nov 28 PM (13:00 - 14:00)
----------------------------------------

(9) 13:00 - 14:00


----- Break ( 15 min. ) -----

----------------------------------------
Mon, Nov 28 PM (14:15 - 15:55)
----------------------------------------

(10)/VLD 14:15 - 14:40
Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT)

(11)/VLD 14:40 - 15:05
Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT)

(12)/VLD 15:05 - 15:30
Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions
Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT)

(13)/VLD 15:30 - 15:55
Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.)

----------------------------------------
Mon, Nov 28 PM (14:15 - 15:55)
----------------------------------------

(14)/RECONF 14:15 - 14:40
Design for 3-Demensional Sound Processor using a High-Level Synthesis
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.)

(15)/RECONF 14:40 - 15:05
Variable Pipeline Ultra Low-power Coarse Grained Reconfigurable Accelelator
Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano (Keio Univ.)

(16)/RECONF 15:05 - 15:30
A Novel Merge Network for FPGA Sorting Accelerators
Makoto Saitoh, Susumu Mashimo, Thiem Van Chu, Kenji Kise (Tokyotech)

(17)/RECONF 15:30 - 15:55
Hardware implementation of PLC Instructions by high level synthesis
Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT)

----- Break ( 15 min. ) -----

----------------------------------------
Mon, Nov 28 PM (16:10 - 17:40)
----------------------------------------

(18) 16:10 - 17:40


----------------------------------------
Tue, Nov 29 AM (10:05 - 11:45)
----------------------------------------

(19)/RECONF 10:05 - 10:30
(See Japanese page.)

(20)/RECONF 10:30 - 10:55
Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm
Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.)

(21)/RECONF 10:55 - 11:20
Development of power estimation tool for three dimensional FPGA
Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(22)/RECONF 11:20 - 11:45
Preliminary experimental platform for FlexPower FPGA evaluation
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike (AIST)

----------------------------------------
Tue, Nov 29 AM (09:00 - 10:15)
----------------------------------------

(23)/VLD 09:00 - 09:25
Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)
Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.)

(24)/VLD 09:25 - 09:50
Ultra Low Power Reconfigurable Accelerator CC-SOTB2
Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.)

(25)/VLD 09:50 - 10:15
FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit
Koki Ito, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

----------------------------------------
Tue, Nov 29 AM (09:00 - 10:15)
----------------------------------------

(26)/ICD 09:00 - 09:25
Measurement of Vth Variation due to STI Stress and Inverse Narrow Channel Effect at Ultra-Low Voltage in a Variability-Suppressed Process
Yasuhiro Ogasahara, Hanpei Koike (AIST)

(27)/ICD 09:25 - 09:50
Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system
Chihiro Matsui, Yusuke Yamaga, Yusuke Sugiyama, Ken Takeuchi (Chuo Univ.)

(28)/ICD 09:50 - 10:15
EMI Performance of Power Delivery Networks in 3D TSV Integration
Yuuki Araga (AIST), Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda (Kobe Univ.), Katsuya Kikuchi (AIST)

----- Break ( 15 min. ) -----

----------------------------------------
Tue, Nov 29 AM (10:30 - 11:45)
----------------------------------------

(29)/VLD 10:30 - 10:55
Accurate Lithography Simulation Model based on Deep Learning
Yuki Watanabe, Tetsuaki Matsunawa, Taiki Kimura, Shigeki Nojima (Toshiba)

(30)/VLD 10:55 - 11:20
Length Difference Minimization with Exchanging Pin Pair for Set Pair Routing Problem
Shutaro Hara, Kunihiro Fujiyoshi (TUAT)

(31)/VLD 11:20 - 11:45
SADP-Cut Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT)

----------------------------------------
Tue, Nov 29 AM (10:30 - 11:20)
----------------------------------------

(32)/CPM 10:30 - 10:55
[Invited Talk]
Development of Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel Signal Processors by Using Direct Bonding of SOI Layers
Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurasgi, Hiroshi Toshiyoshi, Toshiro Hiramoto (Univ. Tokyo)

(33)/CPM 10:55 - 11:20
[Invited Talk]
IoT時代におけるエッジデバイスのインテリジェント化を支える脳型デバイスの重要性
Yasumitsu Orii (NAGASE & CO., LTD.)

----- Lunch Break ( 75 min. ) -----

----------------------------------------
Tue, Nov 29 PM (13:00 - 14:00)
----------------------------------------

(34)/RECONF 13:00 - 14:00
[Invited Talk]
FPGA Development using HLS for Software Engineers
Kenichiro Mitsuda, Hiroshi Owada, Shinji Yamamoto (ISP)

----------------------------------------
Tue, Nov 29 PM (13:15 - 14:00)
----------------------------------------

(35)/ICD 13:15 - 14:00
[Invited Talk]
Ultra-large-scale ultra-high-speed image display technology and applications
-- Application of Image big data --
Hidemichi Kawase (Kamiens)

----- Break ( 5 min. ) -----

----------------------------------------
Tue, Nov 29 PM (14:05 - 14:35)
----------------------------------------

(36) 14:05 - 14:35


----- Break ( 5 min. ) -----

----------------------------------------
Tue, Nov 29 PM (14:40 - 15:30)
----------------------------------------

(37) 14:40 - 15:30
[Keynote Address]
CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era
Masanao Yamaoka (Hitachi)

----- Break ( 15 min. ) -----

----------------------------------------
Tue, Nov 29 PM (15:45 - 16:30)
----------------------------------------

(38) 15:45 - 16:30
[Keynote Address]
The development of video coding technology and contribution to HD transition
Akira Nakagawa (Fujitsu Labs.)

----- Break ( 15 min. ) -----

----------------------------------------
Tue, Nov 29 PM (16:45 - 17:45)
----------------------------------------

(39) 16:45 - 17:45
[Keynote Address]
Data mining techniques and applications
-- Graph mining and exploratory data analysis --
Makoto Onizuka (Osaka Univ.)

----------------------------------------
Wed, Nov 30 AM (09:00 - 10:40)
----------------------------------------

(40)/DC 09:00 - 09:25
Fast Test Pattern Reordering Based on Weighted Fault Coverage
Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.)

(41)/DC 09:25 - 09:50
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults
Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)

(42)/VLD 09:50 - 10:15
On SAT based test pattern generation for transition faults considering signal activities
Yusuke Matsunaga (Kyushu Univ.)

(43)/DC 10:15 - 10:40
A Method of LRSR Seed Generation for On-chip Fault Diagnosis
Hayato Minamizono, Satoshi Ohtake (Oita Univ.)

----------------------------------------
Wed, Nov 30 AM (09:00 - 10:40)
----------------------------------------

(44)/CPSY 09:00 - 09:25
Development and evaluation of on-chip body bias tuning scheme
Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano (Keio Univ.)

(45)/CPSY 09:25 - 09:50
(See Japanese page.)

(46) 09:50 - 10:15


(47)/CPSY 10:15 - 10:40
A Case for GPU Synchronization Method for Graph Processing Using Remote GPUs
Shin Morishima, Hiroki Matsutani (Keio Univ.)

----- Break ( 15 min. ) -----

----------------------------------------
Wed, Nov 30 PM (10:55 - 12:10)
----------------------------------------

(48)/VLD 10:55 - 11:20
Partitioned Hash-table and Balanced-tree based FIB Architecture
Kenta Shimazaki (Waseda Univ.), Yuta Ukon, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Hidenori Nakazato, Nozomu Togawa (Waseda Univ.)

(49)/VLD 11:20 - 11:45
Malisious tamper detector design with capacitance measurement for IoT devices in operation
Ryosuke Kitayama (Waseda Univ.), Takashi Takenaka (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

(50)/DC 11:45 - 12:10
A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD)

----------------------------------------
Wed, Nov 30 AM (10:55 - 12:10)
----------------------------------------

(51)/ICD 10:55 - 11:20
A Power-saving Method for Real-time HEVC Encoder LSIs
Takayuki Onishi, Yuya Omori, Hiroe Iwasaki, Atsushi Shimizu (NTT)

(52)/ICD 11:20 - 11:45
Shift-Register-Based Single-Flux-Quantum Cache Memory Architecture
Koki Ishida (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono, Koji Inoue (Kyushu Univ.)

(53)/IE 11:45 - 12:10
Keypoint Detection based on Learning to Rank for Robust Image Matching under Resolution Variation
Satoshi Yoshikawa, Keisuke Kameyama (Univ. of Tsukuba)

----- Lunch Break ( 70 min. ) -----

----------------------------------------
Wed, Nov 30 PM (13:20 - 14:10)
----------------------------------------

(54)/VLD 13:20 - 13:45
An aging aware high-level synthesis algorithm with floorplanning
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)

(55)/VLD 13:45 - 14:10
Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis
Daisuke Ishikawa, Kenshu Seto (TCU)

----------------------------------------
Wed, Nov 30 PM (13:20 - 15:00)
----------------------------------------

(56)/ICD 13:20 - 13:45
Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller
-- High-Speed Low-Power Reference-Less SAR-ADC --
Tamakoshi Akira, Masanori Natsui, Takahiro Hanyu (Touhoku Univ.)

(57)/ICD 13:45 - 14:10
Fully Integrated, 100-mV Minimum Input Voltage Converter with Gate-Boosted Charge Pump for Energy Harvesting
Hiroshi Fuketa, Shin-ichi O'uchi, Takashi Matsukawa (AIST)

(58)/ICD 14:10 - 14:35
A study on verification method of stochastic flash A/D converter with FPGA
Shodai Isami, Toshimasa Matsuoka (Osaka Univ)

(59)/ICD 14:35 - 15:00
ReRAM Write Voltage Generator with Low Supply Voltage Operation and Optimized Comparator Bias-Current Scheme for IoT Edge Device
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi (Chuo Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Mon, Jan 23, 2017 - Wed, Jan 25, 2017 (tentative): Hiyoshi Campus, Keio Univ. [Mon, Nov 14], Topics: FPGA Applications, etc

# SECRETARY:
Daisuke Fukuda (Fujitsu Laboratories)
E-mail: d-fukuda@jp.fujitsu.com

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Technical Committee on Component Parts and Materials (CPM) ===
# FUTURE SCHEDULE:

Mon, Dec 12, 2016 - Tue, Dec 13, 2016 (tentative): Kyoto University [Wed, Nov 2], Topics: Nitride semiconductors, optoelectronic devices, and related materials
Mon, Jan 30, 2017 - Tue, Jan 31, 2017: Miyajima-Morino-Yado(Hiroshima) [Wed, Nov 16], Topics: Circuit, Device and Engineering Science

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Dec 15, 2016 - Fri, Dec 16, 2016: Tokyo Institute of Technology [Tue, Oct 18]
Mon, Jan 30, 2017 - Tue, Jan 31, 2017: Miyajima-Morino-Yado(Hiroshima) [Wed, Nov 16], Topics: Circuit, Device and Engineering Science

# SECRETARY:
Takeshi Yoshida (Hiroshima Univ.)
TEL 082-424-7643,FAX 082-424-7643
E-mail:tyoshida@dsl.hiroshima-u.ac.jp

=== Technical Committee on Image Engineering (IE) ===
# FUTURE SCHEDULE:

Thu, Dec 8, 2016 - Fri, Dec 9, 2016 (tentative): [Thu, Oct 13]
Mon, Feb 20, 2017 - Tue, Feb 21, 2017: Hokkaido Univ. [Wed, Dec 14], Topics: Image Processing, etc.

# SECRETARY:
Yukihiro Bandoh (NTT)
E-mail: ie-kanji2016@mail.ieice.org

=== Technical Committee on Computer Systems (CPSY) ===
# FUTURE SCHEDULE:

Thu, Dec 15, 2016 - Fri, Dec 16, 2016: Tokyo Institute of Technology [Tue, Oct 18]
Mon, Jan 23, 2017 - Wed, Jan 25, 2017 (tentative): Hiyoshi Campus, Keio Univ. [Mon, Nov 14], Topics: FPGA Applications, etc

# SECRETARY:
Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-mail: miyoshi.takashi@jp.fujitsu.com

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/

=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:

Fri, Dec 16, 2016: Sakata Sogo-Bunka Center(Sakata-City) [Wed, Oct 12], Topics: Winter Workshop on safety
Tue, Feb 21, 2017: Kikai-Shinko-Kaikan Bldg. [Wed, Dec 14], Topics: VLSI Design and Test, etc

# SECRETARY:


=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Mon, Jan 23, 2017 - Wed, Jan 25, 2017 (tentative): Hiyoshi Campus, Keio Univ. [Mon, Nov 14], Topics: FPGA Applications, etc

# SECRETARY:
Kazuya Tanigawa
Hiroshima City University,
e-mail: tanigawa@hiroshima-cu.ac.jp

=== Special Interest Group on System Architecture (IPSJ-ARC) ===

# ANNOUNCEMENT:
# Please see the IPSJ-ARC page below:
http://sigarc.ipsj.or.jp/

=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:

Mon, Jan 23, 2017 - Wed, Jan 25, 2017 (tentative): Hiyoshi Campus, Keio Univ. [Mon, Nov 14], Topics: FPGA Applications, etc

# SECRETARY:
Yasuhiro Takashima (University of Kitakyushu)
Email sldm2015@is.env.kitakyu-u.ac.jp

# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2016-11-28 11:08:04


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