IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev RECONF Conf / Next RECONF Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Moritoshi Yasunaga (Univ. of Tsukuba)
Vice Chair: Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary: Yohei Hori (AIST), Nobuya Watanabe (Okayama Univ.)
Assistant: Yoshiki Yamaguchi (Univ. of Tsukuba)

DATE:
Tue, May 29, 2012 09:00 - 18:00
Wed, May 30, 2012 09:00 - 20:30

PLACE:
Okinawa Gender Equality Center(3-11-1 Nishi Naha-shi Okinawa, 900-0036, Japan. http://www.tiruru.or.jp/?page_id=31. Yasunori Osana. +81-98-895-8745)

TOPICS:
Reconfigurable Systems, etc.

----------------------------------------
Tue, May 29 AM Image Processing (1) (09:00 - 10:15)
Chair: Kentaro Sano (Tohoku Univ.)
----------------------------------------

(1) 09:00 - 09:25
An Acceleration of a Graph Cut Segmentation with FPGA
Daichi Kobori, Tsutomu Maruyama (Univ. of Tsukuba)

(2) 09:25 - 09:50
An Imaging Device Control System
Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)

(3) 09:50 - 10:15
FPGA implementation of a video-based real-time pupil detection method
Yuma Hatanaka, Keisuke Dohi, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki City Univ)

----- Break ( 20 min. ) -----

----------------------------------------
Tue, May 29 AM Device Architecture and Performance Assessment Study (10:35 - 11:50)
Chair: Yuetsu Kodama (Univ. of Tsukuba)
----------------------------------------

(4) 10:35 - 11:00
A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.)

(5) 11:00 - 11:25
Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control
Takashi Kawanami (KIT), Masakazu Hioki (AIST), Yohei Matsumoto (Kaiyo Univ.), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)

(6) 11:25 - 11:50
Optimization of PE Array Interconnection on CMA to Reduce Configuration Data
Rie Uno (keio Univ.), Nobuaki Ozaki, Hideharu Amano (Keio Univ.)

----- Lunch Break ( 80 min. ) -----

----------------------------------------
Tue, May 29 PM HPC on Reconfigurable Hardware (13:10 - 14:50)
Chair: Tsutomu Maruyama (Univ. of Tsukuba)
----------------------------------------

(7) 13:10 - 13:35
Implementation and Evaluation of FPGA-based Data Compression Hardware of Floating-Point Data-Stream
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)

(8) 13:35 - 14:00
An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach
Yuki Agou, Yasuaki Ito, Koji Nakano (Hiroshima Univ.)

(9) 14:00 - 14:25
Implementation of Square Root Calculator on Reconfigurable Processor DS-HIE
Takashi Ueda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)

(10) 14:25 - 14:50
Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation
Yoshiaki Kono, Kentaro Sano, Ryotaro Chiba, Satoru Yamamoto (Tohoku Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Tue, May 29 PM Reconfigurable Application (1) (15:10 - 16:25)
Chair: Yoshiki Yamaguchi (Univ. of Tsukuba)
----------------------------------------

(11) 15:10 - 15:35
Hard error avoidance for TMR module using dynamic relocation in an FPGA
Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(12) 15:35 - 16:00
a design of an interconnection system of modules and a control unit of reconfiguration for embedded systems utilizing dynamic reconfiguration
Tomokazu Mizuno, Yoshiaki Kida, Ryo Kamide, Shin Terada, Mitsuyoshi Tokuda, Tomonori Izumi (Ritsumeikan Univ.)

(13) 16:00 - 16:25
An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects
Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Tue, May 29 PM Reconfigurable Application (2) (16:45 - 18:00)
Chair: Yohei Hori (AIST)
----------------------------------------

(14) 16:45 - 17:10
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ)

(15) 17:10 - 17:35
Implementation of delay control methods for FPGA-based digital DC-DC Converters
Yoshihiko Yamabe, Kanako Nakashima, Keisuke Dohi, Kazuma Hamawaki, Kentaro Yamashita, Kazuhiro Kajiwara, Fujio Kurokawa, Yuichiro Shibata, Kiyoshi Oguri (Univ.)

(16) 17:35 - 18:00
Development of Application for Heterogeneous Multi-Core Processor
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.)

----------------------------------------
Wed, May 30 AM Image Processing (2) (09:00 - 10:15)
Chair: Tomonori Izumi (Ritsumeikan Univ.)
----------------------------------------

(17) 09:00 - 09:25
AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD
Haruhisa Tsuyama, Tsutomu Maruyama (Tsukuba Univ.)

(18) 09:25 - 09:50
Proposal and Evaluation of photon mapping acceleration using FPGA
Takuya Kuhara, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.)

(19) 09:50 - 10:15
Real-time Corner and Polygon Detection System on FPGA
Chunmeng Bi, Tsutomu Maruyama (Univ. of Tsukuba)

----- Break ( 20 min. ) -----

----------------------------------------
Wed, May 30 AM High-Level Synthesis and Development Environment (10:35 - 12:15)
Chair: Yuichiro Shibata(Nagasaki Univ.)
----------------------------------------

(20) 10:35 - 11:00
SOM-based FPGA Placement Method using Shimbel Index
Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(21) 11:00 - 11:25
A Study of HW/SW Co-design with JavaRock
Takefumi Miyoshi, Satoshi Funada (e-trees)

(22) 11:25 - 11:50
A Domain Specific Language and Toolchain for Runtime Binary Acceleration
Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.)

(23) 11:50 - 12:15
A Hardware Implementation and an FPGA Prototyping of a Connect-6 Player Algorithm Using Impulse-C
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.)

----- Lunch Break ( 60 min. ) -----

----------------------------------------
Wed, May 30 PM FPGA Design Contest (13:15 - 16:50)
Chair: Hideharu Amano(Keio Univ.)
----------------------------------------

(1) 13:15 - 14:50
FPGA Design Contest
(opening session and Connect-6 preliminary round)
For details, please visit the following website:
http://www.cs.tsukuba.ac.jp/~yoshiki/FPGA/Contest_eng/

----- Break ( 10 min. ) -----

(2) 15:00 - 16:50
FPGA Design Contest
(Connect-6 final round and closing session)

----- Break ( 25 min. ) -----

----------------------------------------
Wed, May 30 PM Industrial Keynote (17:15 - 18:15)
----------------------------------------

(1) 17:15 - 18:15
DAPDNA: A Coarse-Grained Dynamically Reconfigurable Architecture
-- introduction of application examples and a new product --
Akifumi Watanabe(Tokyo Keiki, Inc.)
http://www.tokyo-keiki.co.jp/hyd/e/products/20120508_dap01.html

----------------------------------------
Wed, May 30 PM FPGA Design Contest Award Ceremony (19:00 - 20:30)
----------------------------------------

(1) 19:00 - 20:30
FPGA Design Contest: Poster Session and Awards Ceremony
http://www.isheart.org/HEART2012/
(The workshop site closes at 21:00.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on Reconfigurable Systems (RECONF) ===

# SECRETARY:
Yoshiki YAMAGUCHI
University of Tsukuba, Japan
E-mail: ba
TEL: 029-853-5760
FAX: 029-853-5760


Last modified: 2012-05-24 00:25:16


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to RECONF Schedule Page]   /  
 
 Go Top  Go Back   Prev RECONF Conf / Next RECONF Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan