IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   / Next ICD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

===============================================
Technical Committee on Integrated Circuits and Devices (ICD)
Chair: MIchitaka Kameyama Vice Chair: Masao Nakaya
Secretary: Kunio Uchiyama, Shinji Miyano
Assistant: Masanori Hariyama, Koji Kai

===============================================
Technical Committee on Signal Processing (SIP)
Chair: Tetsuro Fujii Vice Chair: Kenji Nakayama, Ichiro Kuroda
Secretary: Takayuki Nakachi, Eisuke Horita

===============================================
Technical Committee on Image Engineering (IE)
Chair: Makoto Endoh Vice Chair: Kiyoharu Aizawa, Hiroyuki Imaizumi
Secretary: Ryoichi Kawada, Hirohisa Jozawa
Assistant: Toshiaki Fujii, Akira Utsumi

===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)


DATE:
Thu, Oct 21, 2004 09:30 - 16:40
Fri, Oct 22, 2004 09:20 - 16:40

PLACE:


TOPICS:


----------------------------------------
Thu, Oct 21 AM (09:30 - 12:15)
----------------------------------------

(1) 09:30 - 09:55
Scratch Noise Reduction of SP record utilizing Generalized Harmonic Analysis
Ryuji Takamizawa, Kenji Katayama, Yoshihiro Kanda, Teruo Muraoka (Musashi Inst. of Tech)

(2) 09:55 - 10:20
A Pitch Detection Method for Musical Tones Using Musical Scale Separation Filters
Yu Suzuki, Kohei Otake (Hosei Univ.)

(3) 10:20 - 10:45
Nonlinear Adaptive Equalizer Using Dummy Variables
Takehisa Nagase (Chuo Univ.), Toshihiro Furukawa (Tokyo Univ. of Sience), Kiyoshi Furuya (Chuo Univ.)

----- Break ( 15 min. ) -----

(4) 11:00 - 11:25
Detection of the difficult colors for discrimination by dichromats and color transform for the legibility of color images based on confusion loci theory and color-defective vision models
Mitsuhiko Meguro, Chihiro Takahashi, Toshio Koga (Yamagata Univ.)

(5) 11:25 - 11:50
Shot Change Detection and Camerawork Estimation for Old Film Restoration
Mizuki Hagiwara, Masahide Abe, Masayuki Kawamata (Tohoku Univ.)

(6) 11:50 - 12:15
Robust Flicker Parameter Estimation for Motion in Old Film Sequences
Youji Hamaguchi, Masahide Abe, Masayuki Kawamata (Tohoku Univ.)

----------------------------------------
Thu, Oct 21 PM (13:00 - 16:40)
----------------------------------------

(7) 13:00 - 13:25
Power-Minimum Frequency/Voltage Cooperative Management Method in Sub-decimicron Era
Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.)

(8) 13:25 - 13:50
Fast Motion Vector Estimation employing Adaptively Assigned Search Area Sizes Followed by Hierarchical Sub-Sampling-Block-Matching
Koutarou Oguma, Mitsuhiro Kitani, Tadayoshi Enomoto (Chuo Univ.)

(9) 13:50 - 14:15
"Multi-Step Breaking-off-Search(MS-BOS)" Motion Estimation Algorithm and Low-PowerCMOS-ME LSI
Syouta Hasegawa, Tadayoshi Enomoto (Chuo Univ.)

(10) 14:15 - 14:40
Development of H.264 Decoder Using Low Power DSP
Kenji Goto, Hirofumi Aoki, Atsushi Hatabu (NEC), Shinichi Yamada, Taketsugu Matsubara (NEC Micro Systems), Takashi Miyazaki (NEC)

----- Break ( 20 min. ) -----

(11) 15:00 - 15:25
An Optically Differential Reconfigurable Gate Array using a 0.18 um CMOS process
Minoru Watanabe, Fuminori Kobayashi (Kyushu Institute of Technology)

(12) 15:25 - 15:50
Noise and process variation-tolerant multi-ported register file using 130 nm technology
Yuuichirou Ikeda, Masaya Sumita (Matsushita Electric Industrial)

(13) 15:50 - 16:40
[Invited Talk]
--
-- (SK-Electronics)

----------------------------------------
Fri, Oct 22 AM (09:20 - 12:05)
----------------------------------------

(14) 09:20 - 09:45
3D Graphics Processor for Mobile Set based on Configurable Processor
Takashi Takemoto, Yasuharu Takenaka, Tsutomu Minagawa, Tomohiro Koizumi, Yasuyuki Ushijima, Naoaki Yanagida, Yasuo Ohara, Kouichi Tanaka, Yasuhiko Fujita (Toshiba Corp.)

(15) 09:45 - 10:10
JPEG 2000 codec IP with reduced circuit volume for VGA-video
Taro Hagiya (Fujitsu lab.), Sou Nakamura, Akira Genba, Takashi Kuwahara (FDI), Hiroshi Nakayama (Fujitsu lab.)

(16) 10:10 - 10:35
An Image Recognition Processor Using Dynamically Reconfigurable ALU
Naoto Miyamoto, Koji Kotani (Tohoku University), Kazuyuki Maruo (Advantest), Tadahiro Ohmi (Tohoku University)

----- Break ( 15 min. ) -----

(17) 10:50 - 11:15
A DSP Engine for an Extensible Media Embedded Processor
Toshiyuki Furusawa (Toshiba Microelectronics), Satoshi Inoue, Isao Katayama, Yoshihisa Arai, Masataka Matsui, Meisei Nishikawa, Takeshi Yoshimoto (Toshiba)

(18) 11:15 - 11:40
Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure (Hitachi), Seiji Takeuchi (Renesas), Yuichi Abe, Hiromichi Yamada (Hitachi), Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka (Renesas), Takanori Shimura (Hitachi)

(19) 11:40 - 12:05
A 0.13um CMOS Ultra-compact DVD SoC employing a Full Digital Equalizing PRML Read Channel
Akira Yamamoto, Kouichi Nagano, Koji Okamoto, Hiroki Mouri, Akira Kawabe, Takashi Morie, Hiroyuki Nakahira, Minoru Ochiai (Matsushita Electric Industrial Co.,Ltd.), Youichi Ogura (Matsushita Kotobuki Electronics Industries, Ltd.), Toshihiko Takahashi, Toru Kakiage, Masao Takiguchi, Takashi Yamamoto, Hiroshi Kamiyama, Yutaka Katabe (Matsushita Electric Industrial Co.,Ltd.)

----------------------------------------
Fri, Oct 22 PM (13:00 - 16:40)
----------------------------------------

(20) 13:00 - 13:25
SoC debug architecture and applications
Tomoyuki Kodama, Makoto Saen (Hitachi), Junichi Nishimoto (Renesas), Fumio Arakawa (Hitachi)

(21) 13:25 - 13:50
IEEE802.11a Based Wireless A/V Data Transmission System
Takashi Wakutsu, Naohisa Shibuya, Eiji Kamagata, Takaaki Matsumoto, Yasushi Nagahori, Takafumi Sakamoto, Yasuo Unekawa, Kiyohito Tagami, Mutsumu Serizawa (Toshiba)

(22) 13:50 - 14:15
Implementation of IEEE802.11i Cipher Algorithms for Embedded Systems
Motoki Kimura, Yukio Mitsuyama, Takao Onoye (Osaka Univ.), Isao Shirakawa (Hyogo Univ.)

(23) 14:15 - 14:40
A class-D amplifier using a spectrum shaping technique
Akira Yasuda (Hosei Univ.), Takashi Kimura, Koichiro Ochiai, Toshihiko Hamasaki (TI Japan)

----- Break ( 20 min. ) -----

(24) 15:00 - 15:25
Improvement of Free Viewpoint VoD System by Introducing Curved Dynamic Background Buffering
Akio Ishikawa, Atsushi Matsumura, Ryoichi Kawada, Atsushi Koike (KDDI Labs.)

(25) 15:25 - 15:50
A Global Routing Problem Generation Method based on Rent's Rule
Kazuhide Takatsuji, Yoichi Shiraishi (Gunma Univ.)

(26) 15:50 - 16:15
Bus architecture optimization method for IP-based design
Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)

(27) 16:15 - 16:40
Design of Cell Assignment Circuit for Dynamic Reconstruction
Yutaka Koseki, Akinori Kanasugi (Tokyo Denki Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Wed, Dec 1, 2004 - Thu, Dec 2, 2004: Kitakyushu International Conference Center [Mon, Sep 6]
Thu, Dec 16, 2004 - Fri, Dec 17, 2004: [Fri, Oct 22]
Thu, Jan 27, 2005 - Fri, Jan 28, 2005: Kikai-Shinko-Kaikan Bldg. [Mon, Nov 22]

# SECRETARY:
Kunio Uchiyama (Hitachi)
TEL +81-42-323-1111 (etx. 3701), FAX +81-42-327-7737
E-mail: uchiyama@crl.hitachi.co.jp

=== Technical Committee on Signal Processing (SIP) ===
# FUTURE SCHEDULE:

Dec, 2004: Recess
Thu, Jan 20, 2005 - Fri, Jan 21, 2005: Nagoya Institute of Technology [Tue, Nov 16], Topics: Signal Processing, etc.

# SECRETARY:
Takayuki Nakachi(NTT Network Innovation Laboratories)
TEL046-859-2589,FAX046-859-3014
E-mail:nakachi.takayuki@lab.ntt.co.jp

=== Technical Committee on Image Engineering (IE) ===
# FUTURE SCHEDULE:

Thu, Nov 25, 2004 - Fri, Nov 26, 2004: [Wed, Sep 15]
Thu, Dec 9, 2004 - Fri, Dec 10, 2004: Nagoya University [Fri, Oct 15], Topics: Image coding, streaming technologies for real-time communications, etc.
Mon, Jan 10, 2005 - Tue, Jan 11, 2005: [Sat, Sep 18]
Thu, Feb 3, 2005 - Fri, Feb 4, 2005: [Mon, Nov 15]

# SECRETARY:
Ryoichi Kawada (KDDI R&D Laboratories)
TEL049-278-7427,FAX049-278-7439
E-mail:kawada@kddilabs.jp,ie-kanji@mail.ieice.org

=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:

Wed, Dec 1, 2004 - Thu, Dec 2, 2004: Kitakyushu International Conference Center [Mon, Sep 6]
Tue, Jan 25, 2005 - Wed, Jan 26, 2005: [Wed, Nov 17], Topics: FPGA and its Application, etc


Last modified: 2004-08-31 13:20:08


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to IE Schedule Page]   /   [Return to SIP Schedule Page]   /   [Return to ICD Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 
 Go Top  Go Back   / Next ICD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan