Tue, Jan 28 AM 08:30 - 10:10 |
(1) RECONF |
08:30-08:55 |
Design and implementation of high-level synthesis compiler for stream computation |
Ryo Ito, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(2) RECONF |
08:55-09:20 |
A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs |
Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) |
(3) RECONF |
09:20-09:45 |
Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench |
Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Takuji Mitsuishi, Hideharu Amano (Keio Univ.) |
(4) RECONF |
09:45-10:10 |
a discussion on hardware architecture of SIFT algorithm for FPGAs utilizing a high-level synthesis tool |
Naohisa Arakawa, Lin Meng, Tomonori Izumi (Ritsumeikan Univ.) |
|
10:10-10:25 |
Break ( 15 min. ) |
Tue, Jan 28 AM 10:25 - 12:05 |
(5) CPSY |
10:25-10:50 |
A Storing and Regenerating Signal Information in a Scalable Hardware System |
Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) |
(6) CPSY |
10:50-11:15 |
Hardware Expansion Protocol in a Scalable Hardware System |
Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) |
(7) CPSY |
11:15-11:40 |
A FPGA/GPU cooperation in nodes communication using PEACH2 |
Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Tokyo Univ.), Hideharu Amano (Keio Univ.), Taisuke Boku (Univ. of Tsukuba) |
(8) CPSY |
11:40-12:05 |
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption |
Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) |
|
12:05-13:20 |
Lunch ( 75 min. ) |
Tue, Jan 28 PM 13:20 - 14:20 |
(9) |
13:20-14:20 |
[Invited Talk]
Research on VLSI Circuits
-- From Solving Problem to Creating Future -- |
Tadahiro Kuroda (Keio Univ.) |
|
14:20-14:35 |
Break ( 15 min. ) |
Tue, Jan 28 PM 14:35 - 16:15 |
(10) CPSY |
14:35-15:00 |
The Improvement of Auto-Sharding in MongoDB with Priority-Chunk |
Yasuhiro Sato, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.) |
(11) CPSY |
15:00-15:25 |
Improving the Preformance of Virtual Machine Live Migration by Ordering Memory Page Transfer on Access Pattern |
Shintaro Nakai, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.) |
(12) CPSY |
15:25-15:50 |
A Vertical Link On/Off Algorithm for Wireless 3-D NoCs |
Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
(13) CPSY |
15:50-16:15 |
A Case for Low-Power Networks using FSO and On/Off Links |
Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
|
16:15-16:30 |
Break ( 15 min. ) |
Tue, Jan 28 PM 16:30 - 18:10 |
(14) RECONF |
16:30-16:55 |
A 3D FPGA-Array "Vocalise" and its communication system. |
Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Akihiro Sorimachi, Baku Ogasawara, Masatoshi Sekine (TUAT) |
(15) RECONF |
16:55-17:20 |
An Image Recognition System with Multi-Resolutional Feature Learning on the 3D FPGA-Array "Vocalise" |
Baku Ogasawara, Satoru Yokota, Jiang Li, Yusuke Atsumari, Hiromasa Kubo, Masatoshi Sekine (TUAT) |
(16) RECONF |
17:20-17:45 |
Double Caching Memcached Accelerator |
Eric Shun Fukuda, Tsunaki Sadahisa (Hokkaido Univ.), Hiroaki Inoue, Takashi Takenaka (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) |
(17) RECONF |
17:45-18:10 |
A study on module allocation in multi-FPGA systems |
Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus) |
Wed, Jan 29 AM 08:30 - 10:10 |
(1) CPSY |
08:30-08:55 |
An Experimental Bit-Parallel Solution to Accelerate Smith-Waterman Algorithm |
Saori Sudo, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) |
(2) CPSY |
08:55-09:20 |
Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA |
Satoshi Haramura, Hiroto Kagotani, Yasuyuki Nogami, Yuji Sugiyama (Okayama Univ.) |
(3) CPSY |
09:20-09:45 |
Performance Evaluation of Graph Database using Multicore and GPU |
Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(4) CPSY |
09:45-10:10 |
An Efficient SIMD Instruction set for Motion Estimation |
Ken Miura, Takumi Inomata, Toshio Kondo, Takahiro Sasaki (Mie Univ.) |
|
10:10-10:25 |
Break ( 15 min. ) |
Wed, Jan 29 AM 10:25 - 12:05 |
(5) RECONF |
10:25-10:50 |
Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array |
Toru Katagiri, Hideharu Amano (Keio Univ.) |
(6) RECONF |
10:50-11:15 |
A configurable switch mechanism for random NoCs |
Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
(7) RECONF |
11:15-11:40 |
Implementation and Evaluation of Multi-stream Bandwidth Compressor |
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(8) RECONF |
11:40-12:05 |
Study of accelerator connection using the peripheral bus of OpenMSP430 |
Ayano Fukuju, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) |
|
12:05-13:20 |
Lunch ( 75 min. ) |
Wed, Jan 29 PM 13:20 - 14:35 |
(9) VLD |
13:20-13:45 |
A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems |
Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT) |
(10) VLD |
13:45-14:10 |
On Boolean Matching of LUT-based Circuits |
Yusuke Matsunaga (Kyushu Univ.) |
(11) VLD |
14:10-14:35 |
Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency |
Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.) |
|
14:35-14:50 |
Break ( 15 min. ) |
Wed, Jan 29 PM 14:50 - 16:05 |
(12) VLD |
14:50-15:15 |
Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA |
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
(13) VLD |
15:15-15:40 |
A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design |
Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) |
(14) VLD |
15:40-16:05 |
Methodology for NBTI measurement using an on-chip leakage monitor circuit |
Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.) |
|
16:05-16:20 |
Break ( 15 min. ) |
Wed, Jan 29 PM 16:20 - 17:35 |
(15) VLD |
16:20-16:45 |
PerCUDA: CUDA Binding Framework for Perl |
Takayuki Fukumoto, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(16) VLD |
16:45-17:10 |
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU |
Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(17) |
17:10-17:35 |
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