| Conference Date |
Mon, Sep 26, 2011 14:00 - 17:35
Tue, Sep 27, 2011 09:20 - 12:00 |
| Topics |
Physical-level Design, etc. |
| Conference Place |
University-Business Innovation Center, the University of Aizu |
| Address |
Tsuruga, Ikki-machi, Aizu-Wakamatsu City Fukushima, 965-8580 Japan |
| Transportation Guide |
10 Minute by bus or Taxi from JR Aizuwakamatsu Station. (Bus is not frequent, Check the time table))
http://www.u-aizu.ac.jp/e-access.html |
Contact
Person |
Prof. Yukihide Kohira
+81-242-37-2776 (Conference Venue) |
| Sponsors |
This conference is co-sponsored by the IEEE CAS Japan Chapter
|
| Announcement |
Please join the party at the first night. |
| It is comfortable to take the rapid train "Aizu" between Kooriyama and Aiduwakamatsu. |
| Please check the bus schedule from Aizuwakamatsu Station. Bus is not frequent. |
Mon, Sep 26 PM
14:00 - 15:15 |
| (1) |
14:00-14:25 |
A transistor-level symmetrical layout generation method for analog device |
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| (2) |
14:25-14:50 |
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects |
Yu Zhang, Gong Chen, Qing Dong, Jing Li, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| (3) |
14:50-15:15 |
MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space |
Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Mon, Sep 26 PM
15:30 - 16:20 |
| (4) |
15:30-15:55 |
Analytical Placement for Closed-Symmetrical Placement |
Yasuhiro Takashima, Yusuke Oya (Univ. of Kitakyushu) |
| (5) |
15:55-16:20 |
On set pair routing problem |
Atsushi Takahashi (Osaka Univ.) |
| |
16:20-16:35 |
Break ( 15 min. ) |
Mon, Sep 26 PM
16:35 - 17:35 |
| (6) |
16:35-17:35 |
[Invited Talk]
Bondage: A legal interconnect to define a reasonable placement |
Yoji Kajitani (Univ. of Kitakyushu) |
Tue, Sep 27 AM
09:20 - 10:35 |
| (7) |
09:20-09:45 |
A Reconfigurable Layout Method and Evaluation for Network on Chip |
Yuichi Nakamura (NEC) |
| (8) |
09:45-10:10 |
Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD |
Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) |
| (9) |
10:10-10:35 |
A Design Method of Network-on-Chip Architecture for FPGA |
Hideki Katabami, Hiroshi Saito (Aizu Univ.) |
| |
10:35-10:45 |
Break ( 10 min. ) |
Tue, Sep 27 AM
10:45 - 12:00 |
| (10) |
10:45-11:10 |
A statistical evaluation of approximate methods for soft error tolerance analysis of combinational circuits |
Hidenori Ayabe, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) |
| (11) |
11:10-11:35 |
Acceleration of Smith-Waterman Algorithm using a Pipelined Array Processor |
Asuka Tanaka, Shizuka Ishikawa, Toshiaki Miyazaki (Univ. of Aizu) |
| (12) |
11:35-12:00 |
Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis |
Keisuke Inoue, Mineo Kaneko (JAIST) |
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