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Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Conference Date Thu, Sep 19, 2019 13:00 - 17:20
Fri, Sep 20, 2019 10:00 - 15:00
Topics Reconfigurable Systems, etc. 
Conference Place  
Transportation Guide https://convention-a.jp/kokusai-kaigi/
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF.

Thu, Sep 19 PM  Invited Talk
Chair: Yuichiro Shibata(Nagasaki Univ.)
13:00 - 14:00
(1) 13:00-13:40 [Invited Talk]
Utilization of Cloud FPGA
Takashi Ogawa (AWS)
  13:40-14:00 Break ( 20 min. )
Thu, Sep 19 PM  Design Technology
Chair: Yuki Kobayashi(NEC)
14:00 - 15:00
(2) 14:00-14:20 A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech)
(3) 14:20-14:40
(4) 14:40-15:00 Study of logic element placement algorithm with cost function by neural network Tokio Kamada, Atsushi Kubota, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
  - Break
Thu, Sep 19 PM  Design Experience (1)
Chair: Kazuya Tanigawa(Hiroshima City Univ.)
15:20 - 16:20
(5) 15:20-15:40
(6) 15:40-16:00 Implementation of OpenCL-Based FPGA Accelerator for Polynomial Regression Kentaro Katayama (FUJITSU LAB.)
(7) 16:00-16:20 The Implementation of Binarized YOLO System on Low-cost FPGA Kaijie Wei, Koki Honda, Hideharu Amano (Keio)
  - Break
Thu, Sep 19 PM  Invited Talk (2)
Chair: Kentaro Sano(Tohoku Univ.)
16:40 - 17:20
(8) 16:40-17:20 [Invited Talk]
ZytleBot: Towards FPGA Integration into ROS-based Autonomous Mobile Robots
Yasuhiro Nitta, Sou Tamura, Hideki Takase (Kyoto Univ.)
Fri, Sep 20 AM  Architecture
Chair: Yoshiki Yamaguchi(Tsukuba Univ.)
10:00 - 11:00
(9) 10:00-10:20
(10) 10:20-10:40
(11) 10:40-11:00 Multi-threaded High-Level Synthesis for Bandwidth-intensive Applications Jens Huthmann, Auter Podobas, Takaaki Miyajima, Atsushi Koshiba, Kentaro Sano (RIKEN)
  11:00-11:20 Break ( 20 min. )
Fri, Sep 20 AM  Design Experience (2)
Chair: Masahiro Iida (Kumamoto Univ.)
11:20 - 12:00
(12) 11:20-11:40 FPGA Implementation of Image Recognition with Multiple Simple Neural Networks for Higher Performance and Accuracy Musashi Aoto, Shoya Hirukawa, Yasutaka Wada, Kazutaka Maruyama (Meisei Univ)
(13) 11:40-12:00 Accurate Pedestrian Detection in Thermal Images for FPGA Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara (titech)
  12:00-14:00 Break (Committee Meeting) ( 120 min. )
Fri, Sep 20 PM  Design Technology
Chair: Takefumi Miyoshi(E-trees Japan)
14:00 - 15:00
(14) 14:00-14:20 Quantized Neural Networks Library for Exact Hardware Emulation Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.)
(15) 14:20-14:40
(16) 14:40-15:00 Reconfiguration of " Entropy " Concept in Information Theories
-- Referring to a Biography of Claude Shannon and manuscripts of von Neumann --
Kumon Tokumaru (Writer)

Announcement for Speakers
General TalkEach speech will have 15 minutes for presentation and 5 minutes for discussion.
Invited TalkEach speech will have 30 minutes for presentation and 10 minutes for discussion.

Contact Address and Latest Schedule Information
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Yuichiro Shibata(Nagasaki Univ.)
E--mail: bacis-u 
Announcement http://www.ieice.org/~reconf/


Last modified: 2019-09-04 17:15:51


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