Fri, Feb 8 AM
09:00 - 10:15 |
| (1) |
09:00-09:25 |
ESD/Latch up Failure Analysis of CMOS LSI
-- Failure Mode Analysis with Atutual Data -- |
Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| (2) |
09:25-09:50 |
Fault Diagnosis for Dyinamic Open Faults with Considering Adjacent Lines |
Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Syuhei Kadoyama, Tetsuya Watanabe, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Kouji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) |
| (3) |
09:50-10:15 |
Diagnostic Test Generation for Transition Faults |
Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Toru Kikkawa, Yuzo Takamatsu (Ehime Univ.) |
| |
10:15-10:25 |
Break ( 10 min. ) |
Fri, Feb 8 AM
10:25 - 12:05 |
| (4) |
10:25-10:50 |
Test Generation Method for Full Scan Circuit Using Multi Cycle Capture Test |
Yusho Omori, Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Koji Yamazaki (Meiji Univ.) |
| (5) |
10:50-11:15 |
A variable n-detection test generation method to increase fault sensitization coverage and evaluation of its test quality |
Takeshi Tomita, Toshinori Hosokawa (Nihon University), Koji Yamazaki (Meiji University) |
| (6) |
11:15-11:40 |
Note on Test Power Reduction for Scan-Based Hybrid BIST |
Akifumi Suto, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
| (7) |
11:40-12:05 |
Secure Scan Design Based on Ballanced Structure |
Muneo Hasegawa, Michiko Inoue, Hideo Fujiwara (NAIST) |
| |
12:05-13:00 |
Lunch Break ( 55 min. ) |
Fri, Feb 8 PM
13:00 - 14:40 |
| (8) |
13:00-13:25 |
Fault Secure Property for Soft Error on FPGA Using Two-Rail Logic |
Takehiro Miura, Kazuteru Namba, Hideo Ito (Chiba Univ.) |
| (9) |
13:25-13:50 |
Test Generation for Two-phase Dual-rail Circuits Based on Time Expansion of C-elements |
Masaaki Takegahara, Tsuyoshi Iwagaki, Mineo Kaneko (JAIST) |
| (10) |
13:50-14:15 |
Synthesis of Fault Secure Datapaths with DFG Restructuring |
Hirotaka Shiomichi (Hiroshima City Univ.), Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City) |
| (11) |
14:15-14:40 |
An evaluation of encryption LSI testability against scan based attack |
Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ.) |
| |
14:40-14:50 |
Break ( 10 min. ) |
Fri, Feb 8 PM
14:50 - 16:05 |
| (12) |
14:50-15:15 |
RTL False Path Identification Using High Level Synthesis Information |
Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
| (13) |
15:15-15:40 |
A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint |
Ryoichi Inoue, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) |
| (14) |
15:40-16:05 |
Comparison of exact solutions and greedy solutions in static test compaction |
Kei Yagisawa, Koji Yamazaki (Meiji Univ.), Toshinori Hosokawa (Nihon Univ.), Hisao Tamaki (Meiji Univ.) |
Fri, Feb 8 PM
16:05 - 17:45 |
| (15) |
16:05-16:30 |
Current dissipation of Test pattern generators using ATPG vectors |
Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa (Tokai univ.) |
| (16) |
16:30-16:55 |
Note on Testing of RF Transmitter Considering Component Variation |
Tatsuro Endo, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
| (17) |
16:55-17:20 |
Fault Diagnosis of Analog Circuits by Using Multiple Transistors and Data Samplings |
Jiro Kato, Yukiya Miura (Tokyo Metropolitan Univ.) |
| (18) |
17:20-17:45 |
A Self-Correction Method for Periodic Signals |
Yukiya Miura (Tokyo Metropolitan Univ.) |