Tue, Apr 21 AM
11:00 - 11:50 |
| (1) |
11:00-11:25 |
Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults |
Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| (2) |
11:25-11:50 |
A Development Process with A Model Checking Criterion |
Michitaka Inui (Mitsubishi Electric Micro-Computer Application Software Corp.), Nobukazu Yoshioka (NII) |
| |
11:50-13:00 |
Lunch Break ( 70 min. ) |
Tue, Apr 21 PM
13:00 - 14:15 |
| (3) |
13:00-13:25 |
Evaluation of a Metropolis Algorithm for Constructing Unstructured Overlay Networks |
Tatsushi Takamura, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.) |
| (4) |
13:25-13:50 |
A Security Data-Flow Analysis in the Secure Software Development Environment DFITS |
Fukutomo Nakanishi, Ryotaro Hayashi, Hiroyoshi Haruki, Yurie Fujimatsu, Mikio Hashimoto (Toshiba Corp.) |
| (5) |
13:50-14:15 |
Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units |
Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) |
| |
14:15-14:30 |
Break ( 15 min. ) |
Tue, Apr 21 PM
14:30 - 15:30 |
| (6) |
14:30-15:30 |
[Invited Talk]
Evolution and threat of botnet |
Toshiaki Sudou (NTT Communications) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Tue, Apr 21 PM
15:45 - 17:00 |
| (7) |
15:45-16:10 |
A design of testable response analyzers in built-in self-test |
Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (8) |
16:10-16:35 |
Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design. |
Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) |
| (9) |
16:35-17:00 |
Pulse Propagation Analysis for SER Evaluation of Logic Circuits |
Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) |
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