Wed, Jun 11 PM FPGA Design Contest
Chair: Yasunori Osana
13:30 - 16:50 |
| (1) |
13:30-16:50 |
HEART 2014 Design Contest: Blokus Duo
Please refer to the website for more information:
http://lut.eee.u-ryukyu.ac.jp/dc14/index.html |
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16:50-17:00 |
Break ( 10 min. ) |
Wed, Jun 11 PM Invited talk
Chair: Tetsuo Hironaka (Hiroshima City U.)
17:00 - 17:50 |
| (1) |
17:00-17:50 |
[Invited Talk]
Prospects of Custom Accelerators for Large-Scale Computation
-- Perspectives of Applications, Architectures, and Circuits -- |
Masanori Hariyama (Tohoku Univ.) |
Thu, Jun 12 AM Application
Chair: Kenji Kanazawa (U. Tsukuba)
09:00 - 10:15 |
| (2) |
09:00-09:25 |
A Dynamic Reconfigurable Mixed Analog-Digital Filter
-- Applied to an Acoustic Diagnostic -- |
Hiroki Nakahara, Hideki Yoshida (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Renji Mikami (Mikami Consul.) |
| (3) |
09:25-09:50 |
Optimized HOG for database system |
Mao Hatto, Takaaki Miyajima, Hiroki Matsutani, Hideharu Amano (Keio Univ.) |
| (4) |
09:50-10:15 |
Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm |
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
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10:15-10:25 |
Break ( 10 min. ) |
Thu, Jun 12 AM Architecture and performance assessment study
Chair: Takeshi Ohkawa (Utsunomiya U.)
10:25 - 12:05 |
| (5) |
10:25-10:50 |
Improvement of Implementability by Exploring Routing Architecture in Flex Power FPGA |
Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Hanpei Koike (AIST) |
| (6) |
10:50-11:15 |
An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture |
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
| (7) |
11:15-11:40 |
Three-dimensional FPGA Structure using High-speed Serial Communication |
Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (8) |
11:40-12:05 |
Body bias control of low-power reconfigurable accelerator CMA-SOTB |
Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) |
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12:05-13:45 |
Break ( 100 min. ) |
Thu, Jun 12 PM High-level synthesis and hardware-software codesign
Chair: Yoshiki Yamaguchi (U. Tsukuba)
13:45 - 15:25 |
| (9) |
13:45-14:10 |
A Design of Blokus Player Algorithm with Impulse High-Level Synthesis Tools |
Ryo Kawai, Tomonori Izumi (Ritsumeikan Univ.) |
| (10) |
14:10-14:35 |
Zyndroid: HW/SW Coprocessing Platform for Android Applications |
Susumu Mashimo, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (11) |
14:35-15:00 |
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis |
Koji Okina, Rie Soejima, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| (12) |
15:00-15:25 |
A Study on Accelerating Image Recognition Processing by HW/SW Cooperative Processing on an FPGA for Automatic Watch System on Navigation |
Takeshi Ohkawa (Utsunomiya Univ.), Yohei Matsumoto (Tokyo Marine Univ.), Daichi Uetake, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) |
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15:25-15:35 |
Break ( 10 min. ) |
Thu, Jun 12 PM Acceleration and power performance
Chair: Kazuya Tanigawa（Hiroshima City U.）
15:35 - 17:15 |
| (13) |
15:35-16:00 |
Implementation of a RISC Processor with a Complex Instruction Accelerator
-- Return to a CISC -- |
Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) |
| (14) |
16:00-16:25 |
FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache |
Kenji Kanazawa, Tsutomu Maruyama (Univ. of Tsukuba) |
| (15) |
16:25-16:50 |
Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs |
Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
| (16) |
16:50-17:15 |
A software processor core with variable parallel execution |
Takuya Nagashima, Shoji Tanabe, Yoshiki Yamaguchi (Univ. of Tsukuba) |
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