IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   Prev ICD Conf / Next ICD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Minoru Fujishima (Hiroshima Univ.)
Vice Chair Hideto Hidaka (Renesas)
Secretary Takeshi Yoshida (Hiroshima Univ.), Makoto Takamiya (Univ. of Tokyo)
Assistant Takashi Hashimoto (Panasonic), Masanori Natsui (Tohoku Univ.), Hiroyuki Ito (Tokyo Inst. of Tech.), Pham Konkuha (Univ. of Electro-Comm.)

Conference Date Thu, Apr 20, 2017 10:10 - 17:00
Fri, Apr 21, 2017 09:35 - 15:05
Topics  
Conference Place  
Sponsors This conference is co-sponsored by IEEE SSCS Japan Chapter and IEEE SSCS Kansai Chapter.

Thu, Apr 20 AM 
10:10 - 11:50
(1) 10:10-10:35 [Invited Lecture]
Voltage-Control Spintronics Memory(VoCSM) Having Potentials of Ultra-Low Energy-Consumption and High-Density
Hiroaki Yoda, Naoharu Simomura, Yuichi Osawa, Satoshi Shiratori, Yushi Kato, Iguchi Tomoaki, Yuzou Kamiguchi, Buyandalai Altansargai, Yoshiaki Saito, Katsuhiko Koi, Sugiyama Hideyuki, Souichi Oikawa, Shimizu Mariko, Miaue Ishikawa, Kazutaka Ikegami (Toshiba)
(2) 10:35-11:00 [Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS
Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.)
(3) 11:00-11:50 [Invited Talk]
A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture
Kenji Tsuchida (Toshiba), Kwangmyoung Rho, Dongkeun Kim (SK hynix), Yutaka Shirai (Toshiba), Jihyae Bae (SK hynix), Tsuneo Inaba, Hiromi Noro (Toshiba), Hyunin Moon, Sungwoong Chung (SK hynix), Kazumasa Sunouchi (Toshiba), Jinwon Park, Kiseon Park (SK hynix), Akihito Yamamoto (Toshiba), Seoungju Chung, Hyeongon Kim (SK hynix)
  11:50-13:00 Lunch Break ( 70 min. )
Thu, Apr 20 PM 
13:00 - 14:40
(4) 13:00-13:50 [Invited Talk]
Study on Nano-Dot Structure Permanent Memory
Tsuyoshi Watanabe, Noriyuki Miura, Shijia Liu, Shigeki Imai, Makoto Nagata (Kobe Univ.)
(5) 13:50-14:15 [Invited Lecture]
A 1.0 V Operation NAND Flash Memory Program Voltage Generator Fabricated with Standard CMOS Process and NAND Flash Process for IoT Local Devices
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi (Chuo Univ.)
(6) 14:15-14:40 [Invited Lecture]
TLC NAND Flash Memory Control Techniques to Reduce Errors of Read-Hot and Cold Data for Data Centers
Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.)
  14:40-14:55 Break ( 15 min. )
Thu, Apr 20 PM 
14:55 - 17:00
(7) 14:55-15:20 [Invited Lecture]
First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond
Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi)
(8) 15:20-16:10 [Invited Talk]
Embedded Flash Technology for Automotive Applications
Masaya Nakano, Takashi Ito, Tadaaki Yamauchi, Yasuo Yamaguchi, Takashi Kono, Hideto Hidaka (Renesas Electronics)
(9) 16:10-17:00 [Invited Talk]
A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology
Ryuji Yamashita, Sagar Magia (WDC), Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura (Toshiba), Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang (WDC)
Fri, Apr 21 AM 
09:35 - 11:50
(10) 09:35-10:00 [Invited Lecture]
Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating
Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.)
(11) 10:00-10:25 [Invited Lecture]
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic
Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton Calhoun (UVA), Akihiko Harada (FEA), Kazuyuki Kumeno, Makoto Yasuda, Taiji Ema (MIFS)
(12) 10:25-10:50 [Invited Lecture]
A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time
Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL)
  10:50-11:00 Break ( 10 min. )
(13) 11:00-11:25 [Invited Lecture]
Highly reliable Cu atom switch using thermally tolerant Polymer-solid Electrolyte (TT-PSE) for Nonvolatile Programmable Logic
Koichiro Okamoto, Munehiro Tada, Naoki Banno, Noriyuki Iguchi, Hiromitsu Hada, Toshitsugu Sakamoto, Makoto Miyamura, Yukihide Tsuji, Ryusuke Nebashi, Ayuka Morioka, Xu Bai, Tadahiko Sugibayashi (NEC)
(14) 11:25-11:50 [Invited Lecture]
A 2x Logic Density Programmable Logic Array using Atom Switch
Yukihide Tsuji, Xu Bai, Ayuka Morioka, Miyamura Makoto, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi (NEC)
  11:50-13:00 Lunch Break ( 70 min. )
Fri, Apr 21 PM 
13:00 - 15:05
(15) 13:00-13:25 [Invited Lecture]
High-Density User-Programmable Logic Array Based on Adjacent Integration of Pure-CMOS Crossbar Antifuse into Logic CMOS Circuits
Shinichi Yasuda, Masato Oda, Mari Matsumoto, Kosuke Tatsumura, Koichiro Zaitsu, Ying-Hao Ho, Mizuki Ono (Toshiba)
(16) 13:25-13:50 [Invited Lecture]
Demonstration of HfO2-Based Ferroelectric Tunnel Junction (FTJ)
Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Tsunehiro Ino, Riichiro Takaishi, Yasushi Nakasaki, Masumi Saitoh (Toshiba)
(17) 13:50-14:15 [Invited Lecture]
Embedded Memory and ARM Cortex-M0 Core Using 60-nm CAAC-IGZO FET Integrated with 65-nm Si CMOS
Tatsuya Onuki, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato (Semiconductor Energy Laboratory), T R Yew, Chen Bin Lin, J Y Wu, Chi Chang Shuai, Shao Hui Wu (United Microelectronics Corporation), James Myers (ARM), Klaus Doppler (Nokia Technologies), Masahiro Fujita (The Univ. of Tokyo), Shunpei Yamazaki (Semiconductor Energy Laboratory)
(18) 14:15-15:05 [Invited Talk]
A 1/2.3in 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM
Tsutomu Haruta, Tsutomu Nakajima, Jun Hashizume, Taku Umebayashi, Hiroshi Takahashi, Kazuo Taniguchi, Masami Kuroda, Hiroshi Sumihiro, Koji Enoki (Sony Semiconductor Solutions), Takatsugu Yamasaki (Sony Semiconductor Manufacturing), Katsuya Ikezawa, Atsushi Kitahara, Masao Zen, Masafumi Oyama, Hiroki Koga (Sony Semiconductor Solutions)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.
Invited LectureEach speech will have 20 minutes for presentation and 5 minutes for discussion.
Invited TalkEach speech will have 45 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address  


Last modified: 2017-04-05 19:40:06


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to ICD Schedule Page]   /  
 
 Go Top  Go Back   Prev ICD Conf / Next ICD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan