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Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Vice Chair Hiroshi Takahashi (Ehime Univ.)
Secretary Haruhiko Kaneko (Tokyo Inst. of Tech.), Masayuki Arai (Nihon Univ.)

Conference Date Wed, Feb 27, 2019 09:00 - 16:50
Topics VLSI Design and Test, etc. 
Conference Place Kikai-shinko Kaikan 
Address 3-5-8 Shiba-koen, Minato-ku, Tokyo, 105-0011 Japan
Transportation Guide http://www.jspmi.or.jp/kaigishitsu/access.html
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on DC.

Wed, Feb 27 AM 
09:00 - 10:40
(1) 09:00-09:25 Note on Target Fault Selection for 2-Pattern Test Generation Considering Critical Area Naoya Uchiyama, Masayuki Arai (Nihon Univ.)
(2) 09:25-09:50 Variational Autoencoder-Based Efficient Test Escape Detection Michihiro Shintani (NAIST), Kouichi Kumaki (Renesas Electronics Corporation), Michiko Inoue (NAIST)
(3) 09:50-10:15 A Low Capture Power Oriented X-Identification Method Mimicking Fault Propagation Paths of Capture Safe Test Vectors Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ)
(4) 10:15-10:40 Analysis of the hotspot distribution in the LSI Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech)
  10:40-10:55 Break ( 15 min. )
Wed, Feb 27 AM 
10:55 - 12:10
(5) 10:55-11:20 Efficient Challenge-Response Pairs Generation and Evaluation for PUF Circuit Using BIST Circuit During Manufacturing Test Tomoki Mino, Shintani Michihiro, Michiko Inoue (NAIST)
(6) 11:20-11:45 A built-in self-diagnosis mechanism based on self-generation of expected signatures Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.), Hiroshi Takahashi (Ehime Univ.)
(7) 11:45-12:10 An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling Foisal Ahmed, Michihiro Shintani, Michiko Inoue (NAIST)
  12:10-13:40 Break ( 90 min. )
Wed, Feb 27 PM 
13:40 - 14:55
(8) 13:40-14:05 State Assignment Method to Improve Transition Fault Coverage for Datapath Masayoshi Yoshimura (Kyoto Sangyo Univ.), Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.)
(9) 14:05-14:30 FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas)
(10) 14:30-14:55 A Compaction Method for Test Sensitization State in Controllers Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.)
  14:55-15:10 Break ( 15 min. )
Wed, Feb 27 PM 
15:10 - 16:50
(11) 15:10-15:35 State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines Yuki Maeda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
(12) 15:35-16:00 Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.)
(13) 16:00-16:25
(14) 16:25-16:50 Reliability evaluation of the optical navigation electronics of HAYABUSA2
-- Onboard demonstration of a high reliability system with limited resources --
Hiroki Hihara (NECSpace/NEC), Junpei Sano (NECSpace), Tetsuya Masuda (NEC), Hisashi Otake, Tatsuaki Okada, Naoko Ogawa, Yuichi Tsuda (JAXA)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
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