IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

===============================================
Technical Committee on Dependable Computing (DC)
Chair: Seiji Kajihara (Kyushu Inst. of Tech.) Vice Chair: Nobuyasu Kanekawa (Hitachi)
Secretary: Tomohiro Nakamura (Hitachi), Tatsuhiro Tsuthiya (Osaka Univ.)

DATE:
Fri, Jun 21, 2013 13:45 - 17:00

PLACE:
Kikai-Shinko-Kaikan Bldg.(3-5-8, Shibakoen, Minato-ku, Tokyo, 105-0011 Japan. Tokyo Metro Hibiya Line Kamiyacho Stn. 6min., Toei Subway Mita Line Onarimon Stn. 8min., Toei Subway Oedo Line Akabanebashi Stn. 10min., Toei Subway Asakusa Line / Oedo Line Daimon Stn. 10min., JR Yamanote Line Hamamatsucho Stn. 15 min.http://www.jspmi.or.jp/kaigishitsu/access.html)

TOPICS:
Design, Test, Verification

----------------------------------------
Fri, Jun 21 PM (13:45 - 15:15)
----------------------------------------

(1) 13:45 - 14:15
A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ)

(2) 14:15 - 14:45
A method of deterministic LFSR seed generation for scan-based BIST
Takanori Moriyasu, Satoshi Ohtake (Oita Univ.)

(3) 14:45 - 15:15
A theretical discussion for testabilty of a degraded LSI in field
Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.)

----- Break ( 15 min. ) -----

----------------------------------------
Fri, Jun 21 PM (15:30 - 17:00)
----------------------------------------

(4) 15:30 - 16:00
An Approach of Generating a Test Set to Locate a Pair-Wise Interaction Fault
Takahiro Nagamoto, Hideharu Kojima, Tatsuhiro Tsuchiya (Osaka Univ.)

(5) 16:00 - 16:30
An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Kentaroh Katoh (TNCT)

(6) 16:30 - 17:00
A Method of Transistor Degradation Estimation Using Ring Oscillators
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.)

# Information for speakers
General Talk will have 25 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:

Thu, Aug 1, 2013 - Fri, Aug 2, 2013: Kitakyushu-Kokusai-Kaigijyo [Fri, May 10], Topics: Parallel, Distributed and Cooperative Processing

# SECRETARY:



Last modified: 2013-06-18 10:24:50


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to DC Schedule Page]   /  
 
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan