Thu, Jan 29 AM
08:40 - 09:55 |
| (1) |
08:40-09:05 |
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction |
Toru Sano, Hideharu Amano (Keio Univ) |
| (2) |
09:05-09:30 |
Evaluation of a Multicore Reconfigurable Architecture |
Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.) |
| (3) |
09:30-09:55 |
Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies |
Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) |
| |
09:55-10:05 |
Break ( 10 min. ) |
Thu, Jan 29 AM
10:05 - 11:20 |
| (4) |
10:05-10:30 |
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array |
Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.) |
| (5) |
10:30-10:55 |
FPGA Implementation of Metastability-based True Random Number Generator |
Hisashi Hata, Shuichi Ichikawa (TUT) |
| (6) |
10:55-11:20 |
A Proposal of Message Driven IP Core Interface |
Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| |
11:20-12:20 |
Lunch ( 60 min. ) |
Thu, Jan 29 PM
12:20 - 13:35 |
| (7) |
12:20-12:45 |
A programmable 9-contexts optically reconfigurable gate arrays and its writer |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |
| (8) |
12:45-13:10 |
Perfect demonstration of a four-context Optically Reconfigurable Gate Array |
Takayuki Mabuchi, Minoru Watanabe (Shizuoka Univ.) |
| (9) |
13:10-13:35 |
Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture |
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) |
| |
13:35-13:45 |
Break ( 10 min. ) |
Thu, Jan 29 PM
13:45 - 14:35 |
| (10) |
13:45-14:10 |
Circuit Partition Method with Time-multiplexed I/O |
Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
| (11) |
14:10-14:35 |
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs |
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
| |
14:35-14:45 |
Break ( 10 min. ) |
Thu, Jan 29 PM
14:45 - 16:00 |
| (12) |
14:45-15:10 |
A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length |
Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) |
| (13) |
15:10-15:35 |
Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core |
Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (14) |
15:35-16:00 |
An Experimental Linux Cluster System for Tests |
Koichi Kitano (Polytech.Univ.), Koji Teramoto (EHDO), Tadayoshi Horita (Polytech.Univ.) |
| |
16:00-16:10 |
Break ( 10 min. ) |
Thu, Jan 29 PM
16:10 - 17:50 |
| (15) |
16:10-16:35 |
Extension of High Level Synthesis system CCAP for AMP multi-core system desin |
Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM) |
| (16) |
16:35-17:00 |
A Tunable LSI Based on Timing Skew and Stall Adjustments |
Yayumi Uehara, Mineo Kaneko (JAIST) |
| (17) |
17:00-17:25 |
Fast Module Placement in Floorplan-aware High-level Synthesis |
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (18) |
17:25-17:50 |
A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors |
Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
Fri, Jan 30 AM
08:40 - 09:30 |
| (19) |
08:40-09:05 |
Automatic Equivalence Specification between Two Sequential Circuits in High-level Design |
Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo) |
| (20) |
09:05-09:30 |
Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification |
Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) |
| |
09:30-09:40 |
Break ( 10 min. ) |
Fri, Jan 30 AM
09:40 - 11:20 |
| (21) |
09:40-10:05 |
Foreknown Regularity Arithmetic Processing Unit |
Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| (22) |
10:05-10:30 |
Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm |
Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.) |
| (23) |
10:30-10:55 |
A study for accurate RTL timing modeling |
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.) |
| (24) |
10:55-11:20 |
Interaction of Abstraction Processing for Creation of Ideas
-- An Electronic Brain like a thought of human being -- |
Tadayuki Hattori |
| |
11:20-12:20 |
Lunch ( 60 min. ) |
Fri, Jan 30 PM
Chair: Tohru Ishihara (Kyushu Univ.)
12:20 - 13:35 |
| (25) |
12:20-12:45 |
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems |
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) |
| (26) |
12:45-13:10 |
A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access |
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (27) |
13:10-13:35 |
Combine operation pattern extraction from CDFG for DSP generation |
Toshiyuki Kato, Takaaki Miyake, Shinichi Oomata, Hideto Nishikado, Hironori Yamauchi (Ritsumei Univ), Shiro Kobayashi (Asahi Kasei) |
| |
13:35-13:45 |
Break ( 10 min. ) |
Fri, Jan 30 PM
13:45 - 14:35 |
| (28) |
13:45-14:10 |
Customizing of Domain-Specific and Compact Reconfigurable HW |
Shogo Nakaya, Nobuki Kajihara, Toru Awashima (NEC) |
| (29) |
14:10-14:35 |
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation |
Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.) |
| |
14:35-14:45 |
Break ( 10 min. ) |
Fri, Jan 30 PM
14:45 - 16:00 |
| (30) |
14:45-15:10 |
Implementation of Asynchronous Bus for GALS System |
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| (31) |
15:10-15:35 |
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application |
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (32) |
15:35-16:00 |
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA |
Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ) |
| |
16:00-16:10 |
Break ( 10 min. ) |
Fri, Jan 30 PM
16:10 - 17:25 |
| (33) |
16:10-16:35 |
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation |
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) |
| (34) |
16:35-17:00 |
An FPGA implementation of Gibbs sampling method towards high-speed motif search |
Yuka Sato, Junko Tazawa, Toshiaki Miyazaki (Univ. of Aizu) |
| (35) |
17:00-17:25 |
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2 |
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex) |
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