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=============================================== Technical Committee on Dependable Computing (DC) Chair: Nobuyasu Kanekawa (Hitachi) Vice Chair: Michiko Inoue (NAIST) Secretary: Koji Iwata (RTRI), Tatsuhiro Tsuthiya (Osaka Univ.) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Toshiyuki Shibuya (Fujitsu Labs.) Vice Chair: Yusuke Matsunaga (Kyushu Univ.) Secretary: Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.) Assistant: Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric) =============================================== Technical Committee on Component Parts and Materials (CPM) Chair: Yasushi Takano (Shizuoka Univ.) Vice Chair: Satoru Noge (Numazu National College of Tech.) Secretary: Tomomasa Sato (Kanagawa Univ.), Junichi Kodate (NTT) Assistant: Nobuyuki Iwata (Nihon Univ.), Takashi Sakamoto (NTT) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Takeshi Yamamura (Fujitsu Labs.) Vice Chair: Minoru Fujishima (Hiroshima Univ.) Secretary: Osamu Watanabe (Toshiba) Assistant: Takeshi Yoshida (Hiroshima Univ.), Makoto Takamiya (Univ. of Tokyo), Akira Tsuchiya (Kyoto Univ.), Pham Konkuha (Univ. of Electro-Comm.) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Tsutomu Yoshinaga (Univ. of Electro-Comm.) Vice Chair: Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST) Secretary: Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.) Assistant: Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Tetsuo Hironaka (Hiroshima City Univ.) Vice Chair: Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.) Secretary: Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba) Assistant: Kazuya Tanikagawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Masahiro Fukui (Ritsumeikan Univ.) Secretary: Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.), Masao Yokoyama (Sharp) DATE: Wed, Nov 26, 2014 09:15 - 17:55 Thu, Nov 27, 2014 09:30 - 17:15 Fri, Nov 28, 2014 09:15 - 16:25 PLACE: B-ConPlaza(http://www.b-conplaza.jp/english/) TOPICS: Design Gaia 2014 -New Field of VLSI Design- ---------------------------------------- Wed, Nov 26 AM (09:15 - 10:30) ---------------------------------------- (1)/RECONF 09:15 - 09:40 A study on automated arithmetic pipeline design on multi-FPGA systems Yusuke Hirai, Katsuki Kyan, Makoto Arakaki (Univ. Ryukyus), Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. Ryukyus) (2)/RECONF 09:40 - 10:05 Implementation of Multi-dimensional FPGA array HPC system-Vocalise for Numerical simulation and its Performance Evaluation Jiang Li, Hiromasa Kubo, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT) (3)/RECONF 10:05 - 10:30 Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures Hayate Okuhara, Hideharu Amano (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 AM (10:45 - 12:00) ---------------------------------------- (4)/RECONF 10:45 - 11:10 Mobile robot system based on hw/sw Complex System using 3D FPGA-Array System "Vocalise" Hiromasa Kubo, Jiang Li, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT) (5)/RECONF 11:10 - 11:35 An Image Recognition System Learning Feature Regions with Vocalise Satoru Yokota, Jiang Li, Hiromasa Kubo, Masatoshi Sekine (TUAT) (6)/RECONF 11:35 - 12:00 Efficient FPGA resource allocation for HOG-based human detection Masahito Oishi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) ---------------------------------------- Wed, Nov 26 PM (13:30 - 14:30) ---------------------------------------- (7) 13:30 - 14:30 ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 PM (14:45 - 16:00) ---------------------------------------- (8)/DC 14:45 - 15:10 Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) (9)/VLD 15:10 - 15:35 Analytical placement consistent with hierarchical structure constraints in analog floorplan Shigetoshi Nakatake (Univ. of Kitakyushu) (10)/VLD 15:35 - 16:00 An efficient calculation of RTN-induced SRAM failure probability Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 PM (16:15 - 17:55) ---------------------------------------- (11)/VLD 16:15 - 16:40 General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power Shogo Yamasaki, Toshinobu Akazawa, Fengwei An, Hans Juergen Mattausch (Hiroshima Univ.) (12)/VLD 16:40 - 17:05 An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ.) (13)/VLD 17:05 - 17:30 Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.) (14)/VLD 17:30 - 17:55 Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.) ---------------------------------------- Wed, Nov 26 AM (09:15 - 10:30) ---------------------------------------- (15)/VLD 09:15 - 09:40 Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) (16)/VLD 09:40 - 10:05 Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (17)/VLD 10:05 - 10:30 An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 AM (10:45 - 12:00) ---------------------------------------- (18) 10:45 - 11:10 (19) 11:10 - 11:35 (20) 11:35 - 12:00 ---------------------------------------- Wed, Nov 26 PM (14:45 - 16:00) ---------------------------------------- (21)/CPSY 14:45 - 15:10 Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing Yoshifumi Fujikawa, Tetsuro Hommura, Tadayuki Matsumura (Hitachi) (22)/CPSY 15:10 - 15:35 A Large Graph Segmentation Method for Triangle Counting Tatsuhiro Hirano, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST) (23)/CPSY 15:35 - 16:00 Parallelization of Shortest Path Search on Various Platforms and Its Evaluation Shuto Kurebayashi, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 PM (16:15 - 17:05) ---------------------------------------- (24)/CPSY 16:15 - 16:40 An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) (25)/CPSY 16:40 - 17:05 A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) ---------------------------------------- Wed, Nov 26 AM (10:45 - 12:00) ---------------------------------------- (26)/VLD 10:45 - 11:10 A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) (27)/VLD 11:10 - 11:35 Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) (28)/VLD 11:35 - 12:00 Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) ---------------------------------------- Wed, Nov 26 PM (14:45 - 16:00) ---------------------------------------- (29)/VLD 14:45 - 15:10 A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (30)/VLD 15:10 - 15:35 A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (31)/VLD 15:35 - 16:00 A Method for Total Length and Length Difference Reduction for Set-Pair Routing Yuta Nakatani, Atsushi Takahashi (Titech) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 26 PM (16:15 - 17:55) ---------------------------------------- (32)/VLD 16:15 - 16:40 High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) (33)/VLD 16:40 - 17:05 Don't-Care Extension in Logic Synthesis for Error Tolerant Application Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) (34)/VLD 17:05 - 17:30 Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis Junghoon Oh, Mineo Kaneko (JAIST) (35)/VLD 17:30 - 17:55 A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) ---------------------------------------- Thu, Nov 27 AM (09:30 - 11:30) ---------------------------------------- (36) 09:30 - 11:30 ---------------------------------------- Thu, Nov 27 PM (13:30 - 14:30) ---------------------------------------- (37) 13:30 - 14:30 [Invited Talk] Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect Kagayaki Kuroda (Tokai Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Nov 27 PM (14:45 - 15:45) ---------------------------------------- (38) 14:45 - 15:45 [Invited Talk] Latest Development and Future Prospect of Mobile Display Technology Yoshiharu Nakajima (JDI) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Nov 27 PM (16:00 - 17:15) ---------------------------------------- (39)/VLD 16:00 - 16:25 Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability Mineo Kaneko (JAIST) (40) 16:25 - 16:50 (41)/VLD 16:50 - 17:15 On implicit enumeration of vector pairs for synthesizing index generator Yusuke Matsunaga (Kyushu Univ.) ---------------------------------------- Thu, Nov 27 PM (16:00 - 17:15) ---------------------------------------- (42)/ICD 16:00 - 16:25 Integrated-Circuit Countermeasures Against Side-Channel Information Leakage Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata (Kobe University) (43)/ICD 16:25 - 16:50 Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks Takashi Nishimura, Akihiro Takeuchi, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) (44)/ICD 16:50 - 17:15 Circuit Design of Reconfigurable Dynamic Logic Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (Shonan Inst. of Tech.) ---------------------------------------- Thu, Nov 27 PM (16:00 - 17:15) ---------------------------------------- (45)/RECONF 16:00 - 16:25 Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (46)/RECONF 16:25 - 16:50 Voice Recognition System using hw/sw Complex Yuichi Ogishima, Jiang Li, Satoru Yokota, Hiromasa Kubo, Masatoshi Sekine (TUAT) (47)/RECONF 16:50 - 17:15 Accelerating finite field arithmetic with a suitable word size Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa (Nagasaki Univ.) ---------------------------------------- Fri, Nov 28 AM (09:15 - 10:55) ---------------------------------------- (48)/CPSY 09:15 - 09:40 Scalable and Low Latency Structure for Castle of Chips Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) (49)/CPSY 09:40 - 10:05 A Distributed Router Architecture using transparent latches for Networks-on-Chip Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) (50)/CPSY 10:05 - 10:30 Implementation and Evaluation of An Accelerator based on Manymemory Network Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) (51)/CPSY 10:30 - 10:55 Convolutional Neural Network Processing on An Accelerator based on Manymemory Network Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Nov 28 AM (11:10 - 12:10) ---------------------------------------- (52)/CPSY 11:10 - 12:10 [Fellow Memorial Lecture] Looking Back over My Researches on Flexible Hardware -- Reconfigurable Systems and FPGAs -- Toshinori Sueyoshi (Kumamoto Univ.) ---------------------------------------- Fri, Nov 28 PM (13:30 - 14:30) ---------------------------------------- (53) 13:30 - 14:30 [Invited Talk] A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Nov 28 PM (14:45 - 16:25) ---------------------------------------- (54)/ICD 14:45 - 15:35 [Invited Talk] 25-Gb/s CMOS Optical Transceiver for Board-to-board Interconnects Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka (Hitachi) (55)/ICD 15:35 - 16:25 [Invited Talk] An approach for 30Gb/s optical LSI volume testing Daisuke Watanabe (Advantest), Shin Masuda (ADVANTEST Lab) ---------------------------------------- Fri, Nov 28 AM (09:15 - 10:55) ---------------------------------------- (56)/DC 09:15 - 09:40 Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open Masayuki Arai (Nihon Univ.), Yuta Nakayama, Kazuhiko Iwasaki (Tokyo Metro. Univ.) (57)/DC 09:40 - 10:05 A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) (58)/DC 10:05 - 10:30 A Test Point Insertion Method to Reduce Capture Power Dissipation Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) (59)/DC 10:30 - 10:55 A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) ---------------------------------------- Fri, Nov 28 PM (14:45 - 16:25) ---------------------------------------- (60)/VLD 14:45 - 15:10 A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations Shunya Hosaka, Hiroshi Saito (Univ. Aizu) (61)/VLD 15:10 - 15:35 A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.) (62)/VLD 15:35 - 16:00 Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (63)/VLD 16:00 - 16:25 A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) ---------------------------------------- Fri, Nov 28 AM (09:15 - 10:55) ---------------------------------------- (64)/VLD 09:15 - 09:40 Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (65)/VLD 09:40 - 10:05 Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (66)/VLD 10:05 - 10:30 Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) (67)/VLD 10:30 - 10:55 The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.) ---------------------------------------- Fri, Nov 28 PM (14:45 - 16:25) ---------------------------------------- (68)/DC 14:45 - 15:10 On-chip delay measurement for FPGAs Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT) (69)/DC 15:10 - 15:35 A Method of Burn-in Fail Prediction of LSIs Based on Supervised Learning Using Cluster Analysis Shogo Tetsukawa, Seiya Miyamoto, Satoshi Ohtake (Oita Univ.), Yoshiyuki Nakamura (Renesas) (70)/DC 15:35 - 16:00 Some Studies of n-Fault-Tolerant System with Voting Switches Hitoshi Iwai (71)/DC 16:00 - 16:25 An analytic evaluation on soft error immunity enhancement due to temporal triplication Ryutaro Doi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Dec 19, 2014: [Fri, Oct 17], Topics: Safety, etc. Fri, Feb 13, 2015: Kikai-Shinko-Kaikan Bldg [Mon, Dec 15], Topics: VLSI Design and Test, etc === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Thu, Jan 29, 2015 - Fri, Jan 30, 2015: Hiyoshi Campus, Keio University [Fri, Nov 14], Topics: FPGA Applications, etc # SECRETARY: Noriyuki Minegishi (Mitsubishi Electric Corporation) E-mail:   gi       aj bielectc Tel: 0467-41-2944 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Component Parts and Materials (CPM) === # FUTURE SCHEDULE: Thu, Nov 27, 2014 - Fri, Nov 28, 2014: [Mon, Sep 15] Fri, Feb 27, 2015: NTT Musashino R&D Center [Mon, Dec 8] === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Mon, Dec 1, 2014 - Tue, Dec 2, 2014: Kikai-Shinko-Kaikan Bldg. [Fri, Oct 10] Wed, Dec 3, 2014 - Thu, Dec 4, 2014: Campus Plaza Kyoto , Topics: Technical meeting on Analog RF Thu, Jan 29, 2015 - Fri, Jan 30, 2015: [Thu, Nov 13] # SECRETARY: Takeshi Yoshida (Hiroshima University) TEL:082-424-7643 E-mail:t   dsl   -u === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Mon, Dec 1, 2014 - Tue, Dec 2, 2014: Kikai-Shinko-Kaikan Bldg. [Fri, Oct 10] Thu, Jan 29, 2015 - Fri, Jan 30, 2015: Hiyoshi Campus, Keio University [Fri, Nov 14], Topics: FPGA Applications, etc # SECRETARY: Akira ASATO (FUJITSU) TEL +81-44-754-3233, FAX +81-44-754-3214 E-mail: a       === Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Thu, Jan 29, 2015 - Fri, Jan 30, 2015: Hiyoshi Campus, Keio University [Fri, Nov 14], Topics: FPGA Applications, etc # SECRETARY: Kazuya Tanigawa (Hiroshima City Univ.)     -cu=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Thu, Jan 29, 2015 - Fri, Jan 30, 2015: Hiyoshi Campus, Keio University [Fri, Nov 14], Topics: FPGA Applications, etc # SECRETARY: Makoto Sugihara (Kyushu U) Email sldm2013  caitkshu-u# ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2014-11-20 18:15:00 |
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