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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Kazutoshi Wakabayashi (NEC) Vice Chair: Atsushi Takahashi (Tokyo Inst. of Tech.) Secretary: Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.) =============================================== Technical Committee on Component Parts and Materials (CPM) Chair: Kiichi Kamimura (Shinshu Univ.) Vice Chair: Kanji Yasui (Nagaoka Univ. of Tech.) Secretary: Hidehiko Shimizu (Niigata Univ.), Naoki Oba (NTT) Assistant: Yasushi Takemura (Yokohama National Univ.), Tadayuki Imai (NTT) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Akira Matsuzawa (Tokyo Inst. of Tech.) Vice Chair: Kunio Uchiyama (Hitachi) Secretary: Makoto Nagata (Kobe Univ.), Minoru Fujishima (Univ. of Tokyo) Assistant: Yoshio Hirose (Fujitsu Labs.), Hiroaki Suzuki (Renesas) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Toshinori Sueyoshi (Kumamoto Univ.) Vice Chair: Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi) Secretary: Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.) Assistant: Hidetsugu Irie (Univ. of Tokyo) =============================================== Technical Committee on Dependable Computing (DC) Chair: Takashi Aikyo (STARC) Vice Chair: Tomohiro Yoneda (NII) Secretary: Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) Secretary: Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Yohei Hori (AIST) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Shinji Kimura Secretary: Yutaka Tamiya, Tohru Ishihara, Takashi Aoki DATE: Mon, Nov 17, 2008 13:00 - 17:05 Tue, Nov 18, 2008 09:00 - 16:20 Wed, Nov 19, 2008 10:00 - 17:00 PLACE: Kitakyushu Science and Research Park(2-1 Hibikino, Wakamatsu-ku, Kitakyushu City 808-0135. http://www.ksrp.or.jp/english/access/index.html. Prof. Yasuhiro Takashima. 093-695-3729) TOPICS: Design Gaia 2008 ―New field of VLSI design― ---------------------------------------- Mon, Nov 17 PM (13:00 - 14:40) ---------------------------------------- (1)/DC 13:00 - 13:25 On Improving Transition Fault Coverage of Stuck-at Fault Tests Using Don't Care Identification Technique Kazumitsu Hamasaki, Toshinori Hosokawa (Nihon Univ.) (2)/DC 13:25 - 13:50 An Integer Programming Formulation for Generating High Quality Transition Tests Tsuyoshi Iwagaki, Mineo Kaneko (Japan Advanced Institute of Science and Technology) (3)/DC 13:50 - 14:15 A Capture-Safe Test Generation Scheme for At-speed Scan Testing Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology) (4)/DC 14:15 - 14:40 Analysis of Open Fault using TEG Chip Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) ----- Break ( 20 min. ) ----- ---------------------------------------- Mon, Nov 17 PM (15:00 - 16:40) ---------------------------------------- (5)/VLD 15:00 - 15:25 Area Efficient Multipliers Utilizing the Sum of Operands Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) (6)/VLD 15:25 - 15:50 Hardware Algorithm for Division in GF(2^m) Based on the Extended Euclid's Algorithm Accelerated with Parallelization of Modular Reductions Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ.) (7)/VLD 15:50 - 16:15 Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (8)/VLD 16:15 - 16:40 A Parallel Hardware Engine for Generating Deformed Maps Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ---------------------------------------- Mon, Nov 17 PM (13:00 - 14:15) ---------------------------------------- (9)/VLD 13:00 - 13:25 Scan-based Attack for an AES-LSI included with other IPs Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) (10)/VLD 13:25 - 13:50 Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs Hiroshi Atobe, Ryuta Nara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (11)/VLD 13:50 - 14:15 A Power Masking Method of AES Circuit By Using Cross Bar Switch To Switch S-Box Circuit. Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Nov 17 PM (14:30 - 15:20) ---------------------------------------- (12)/VLD 14:30 - 14:55 On Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design Shimpei Asano, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology) (13)/VLD 14:55 - 15:20 CAFE router: A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) ----- Break ( 20 min. ) ----- ---------------------------------------- Mon, Nov 17 PM (15:40 - 16:55) ---------------------------------------- (14)/DC 15:40 - 16:05 Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) (15)/IPSJ-SLDM 16:05 - 16:30 Insertion-Point Selection of Canary FF for Timing Error Prediction Yuji Kunitake (Kyushu Univ.), Toshinori Sato (Fukuoka Univ.), Seiichiro Yamaguchi, Hiroto Yasuura (Kyushu Univ.) (16)/VLD 16:30 - 16:55 Evaluating the reliability of Highly Reliable Cell Circuits Keiichi Hotta, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) ---------------------------------------- Mon, Nov 17 PM (13:00 - 14:40) Chair: Akira Nagoya (Okayama Univ.) ---------------------------------------- (17)/RECONF 13:00 - 13:25 An emulation experiment of an inversion/non-inversion dynamic optical reconfiguration architecture Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) (18)/RECONF 13:25 - 13:50 Assembly accuracy of a holographic memory in an optically reconfigurable gate array Hironobu Morita, Minoru Watanabe (Shizuoka Univ.) (19)/RECONF 13:50 - 14:15 Preliminary Evaluations of SMA: A Massive Array of Low-Power Reconfigurable Processors Hideharu Amano (Keio Univ.), Kyundong Kim (Tokyo Univ.), Hiroki Matsutani, Vasutan Tunbungheng, Yoshihiro Yasuda (Keio Univ.), Masaaki Kondo (The University of Electro-Communications), Hiroshi Nakamura (Tokyo Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) (20)/RECONF 14:15 - 14:40 A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology) ----- Break ( 20 min. ) ----- ---------------------------------------- Mon, Nov 17 PM (15:00 - 17:05) Chair: Nobuki Kajihara (NEC) ---------------------------------------- (21)/RECONF 15:00 - 15:25 A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (22)/RECONF 15:25 - 15:50 Adaptive routing of the 2-D torus network based on a Turn model Kazuya Matoyama, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) (23)/RECONF 15:50 - 16:15 Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) (24)/RECONF 16:15 - 16:40 Soft Error Mitigation Techniques for FPGA Switch Matrices Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) (25)/RECONF 16:40 - 17:05 Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation Wang Luzhou, Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto (Tohoku Univ.) ---------------------------------------- Tue, Nov 18 AM Design and Test for Computer Systems (10:00 - 11:15) Chair: Yoshio MIKI (HITACHI) ---------------------------------------- (1)/CPSY 10:00 - 10:25 A Path-Based Thread Partitioning Technique Considering Loop Structures Hirohito Ogawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) (2)/CPSY 10:25 - 10:50 Program Behavior Analysis Based on Loop Paths Hideto Yanome, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) (3)/CPSY 10:50 - 11:15 Initial Examination of Detour Routing that uses Global Information Hiroki Mori, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) ----- Break ( 80 min. ) ----- ---------------------------------------- Tue, Nov 18 PM Design and Test for Computer Systems (12:35 - 13:50) Chair: Akira ASATO (FUJITSU) ---------------------------------------- (4)/CPSY 12:35 - 13:00 Decoded Instruction Cache for Server Virtualization Feature Toshiomi Moriki, Naoya Hattori, Yuji Tsushima, Eiichiro Oiwa (Hitachi, Ltd., Central Research Laboratory) (5)/CPSY 13:00 - 13:25 Memory Virtualization Mechanism for Server Virtualization Naoya Hattori, Toshiomi Moriki, Yuji Tsushima, Norimitsu Hayakawa (Hitachi, ltd) (6)/CPSY 13:25 - 13:50 An optimization method for MIMD controlled data communication of MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) ---------------------------------------- Tue, Nov 18 AM (10:30 - 11:20) ---------------------------------------- (7)/VLD 10:30 - 10:55 A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (8)/VLD 10:55 - 11:20 Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) ----- Lunch ( 75 min. ) ----- ---------------------------------------- Tue, Nov 18 PM (13:00 - 13:50) ---------------------------------------- (9)/IPSJ-SLDM 13:00 - 13:25 Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) (10)/IPSJ-SLDM 13:25 - 13:50 Generation of High Coverage Property Set Using Counterexamples Takeshi Matsumoto, Yeonbok Lee, Hiroaki Yoshida (Univ. of Tokyo), Hisashi Yomiya (Toshiba Corporation), Masahiro Fujita (Univ. of Tokyo) ---------------------------------------- Tue, Nov 18 AM (10:30 - 11:45) ---------------------------------------- (11)/DC 10:30 - 10:55 [Poster Presentation] A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) (12)/DC 10:55 - 11:20 [Poster Presentation] A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (13)/DC 11:20 - 11:45 A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology) ---------------------------------------- Tue, Nov 18 AM (09:00 - 10:40) Chair: Hideharu Amano (Keio Univ.) ---------------------------------------- (14)/RECONF 09:00 - 09:50 [Invited Talk] The End of Moore`s Law and the Future of Computing Systems, Probably Krishna V. Palem (Rice Univ.) (15)/RECONF 09:50 - 10:40 [Invited Talk] C-based Programmable-HW Core "STP Engine": Current Status and the Future Masato Motomura (NEC Electronics) ---------------------------------------- Tue, Nov 18 AM (11:00 - 11:45) ---------------------------------------- (16) 11:00 - 11:45 [Invited Talk] Development and evaluation for high-speed and high-performance processor board Yuichi Sato, Takashi Omizo (TOSHIBA Corp.) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Tue, Nov 18 (13:00 - 14:30) ---------------------------------------- (17) 13:00 - 13:45 [Invited Talk] Optimization of Power Integrity in Packaging Design for a High-Performance Microprocessor Shin Suminaga (IIBM Japan, Ltd.) (18) 13:45 - 14:30 [Invited Talk] Thermal design and on-die thermal sensing in the SX supercompurters Mikihiro Kajita, Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno (NEC Corporation) ----- Break ( 20 min. ) ----- ---------------------------------------- Tue, Nov 18 (14:50 - 16:20) ---------------------------------------- (19) 14:50 - 15:35 [Invited Talk] LSI,PCB Co-analysis Technology Toshiro Sato (FUJITSU Advanced Technologies Limited) (20) 15:35 - 16:20 [Invited Talk] PCB design technology for System LSI -- EMC System Design -- Kouji Ichikawa (DENSO CORPORATION) ---------------------------------------- Tue, Nov 18 PM (13:00 - 14:15) Chair: Yohei Hori (AIST) ---------------------------------------- (21)/RECONF 13:00 - 13:25 On Programmable Two-Variable Numerical Function Generators Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (Kyushu Institute of Technology), Jon T. Butler (Naval Postgraduate School) (22)/RECONF 13:25 - 13:50 An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.), Kyrre Glette, Jim Toressen (Oslo Univ.) (23)/RECONF 13:50 - 14:15 A Novel Network Optimization Method using On-Chip Virtual Network on Dynamically Reconfigurable Processor DAPDNA-2 Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio University), Kosuke Shiba (IPFlex Inc) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Nov 18 PM (14:30 - 15:45) Chair: Tomonori Izumi (Ritsumeikan Univ.) ---------------------------------------- (24)/RECONF 14:30 - 14:55 An improvement of Black-Diamond compiler for representing target dynamically reconfigurable architecture Vasutan Tunbunheng, Hideharu Amano (Keio Univ.) (25)/RECONF 14:55 - 15:20 The Experiment of Automatic circuit generation for image processing using extended C code on DRP -- DFC, the Language of Hardware generation for DAPDNA - its issue and solution -- Kazuo Yamada, Takao Naito (Fuji Xerox), Mitsumasa Yoshimura, Jiro Iwai (IPFlex) (26)/RECONF 15:20 - 15:45 Development of Side-channel Attack Standard Evaluation BOard and Tool Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh (National Institute of Advanced Industrial Science and Technology), Hideki Imai (Chuo Univ.) ---------------------------------------- Wed, Nov 19 AM (10:00 - 11:40) ---------------------------------------- (27)/VLD 10:00 - 10:25 Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ.) (28)/VLD 10:25 - 10:50 A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) (29)/VLD 10:50 - 11:15 Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (Japan Advanced Institute of Science and Technology) (30)/VLD 11:15 - 11:40 Enlarging The Solution Spaces For Schedulability Based On Skew Optimization Takayuki Obata, Mineo Kaneko (Japan Advanced Institute of Science and Technology) ---------------------------------------- Wed, Nov 19 AM (10:00 - 11:40) ---------------------------------------- (31)/VLD 10:00 - 10:25 Accuracy and Speed Improvement of Random Walk Simulation Using Walk Sharing and Return-to-Start Transient Analysis Technique Hitoshi Miwa, Goro Suzuki (Univ. of Kitakyushu) (32)/VLD 10:25 - 10:50 Delay analysis method using stochastic process Kazuki Hori, Goro Suzuki (Univ. of Kitakyushu) (33)/VLD 10:50 - 11:15 Power Noise Analysis Acceleration Technique by Linear Programming Method Takeshi Gomakubo, Goro Suzuki (The Univ. of Kitakyushu) (34)/VLD 11:15 - 11:40 Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) ---------------------------------------- Wed, Nov 19 AM (10:50 - 11:40) ---------------------------------------- (35)/ICD 10:50 - 11:15 A Fast Simulation Technique of Processor Power Supply Noise using Capacitance Charging Model Fukuichi Iwasa, Takuya Sawada, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) (36)/ICD 11:15 - 11:40 An On-Chip Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio Susumu Kobayashi, Naoshi Doi (NEC Electronics Corp.) ---------------------------------------- Wed, Nov 19 PM (13:00 - 14:00) ---------------------------------------- (37) 13:00 - 13:30 [Invited Talk] Technologies in the year 2050 Osamu Karatsu (SRI Japan) (38) 13:30 - 14:00 [Invited Talk] Emerging Ubiquitus Wireless Networks Haruhisa Ichikawa (Univ. of Electro-Communications), Hitoaki Sakamoto (NTT), Yuusuke Kawakita, Etsuko Suzuki (Univ. of Electro-Communications) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 19 (14:15 - 17:00) ---------------------------------------- (39) 14:15 - 14:45 [Invited Talk] A Business Model for BOP Hiroto Yasuura (Kyushu Univ.) (40) 14:45 - 15:15 [Invited Talk] The Business Strategy between Vertical Integrated and Vertical Dis-Intergrated Production System on Semiconductor Industry Wang, Shwu Jen (Univ. of Kitakyushu) ----- Break ( 15 min. ) ----- (41) 15:30 - 17:00 [Panel Discussion] Future Prospective of Semiconductor Devices in 2025 -- Based on Ishigaki Workshop by ICD -- Hiroto Yasuura (Kyushu Univ.), Osamu Karatsu (SRI International Japan), Haruhisa Ichikawa (Univ. of Electro-Communications), Wang, Shu Zhen (Univ. of Kitakyushu), Koji Kai (Panasonic), Minoru Fujishima (Univ. of Tokyo) # CONFERENCE ANNOUNCEMENT: - Please join us for a banquet on November 18th after the conference. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Thu, Jan 29, 2009 - Fri, Jan 30, 2009: [Fri, Nov 7] Wed, Mar 11, 2009 - Fri, Mar 13, 2009: [Wed, Jan 14], Topics: Design Technology for a System-on-Silicon # SECRETARY: Ichiro Kohno (Renesas Technology Corp.) E-mail:  h  i      s TEL: +81-42-312-5873 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Component Parts and Materials (CPM) === # FUTURE SCHEDULE: Thu, Nov 27, 2008 - Fri, Nov 28, 2008: Nagoya Institute of Technology [Tue, Sep 9], Topics: Nitride Based Optical and Electronic Devices, Materials and Related Technologies Fri, Jan 23, 2009: Kikai-Shinko-Kaikan Bldg. [Mon, Nov 10] # SECRETARY: Hidehiko Shimizu（Niigata University） TEL 025-262-6811, FAX 025-262-6811 E-mail:    eng i  -u Yasushi Takemura（Yokohama National University） TEL 045-339-4151, FAX 045-339-4151 E-mail:    y === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Thu, Dec 11, 2008 - Fri, Dec 12, 2008: Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan [Mon, Oct 20], Topics: Workshop for Graduate Student and Young Researchers Tue, Jan 13, 2009 - Wed, Jan 14, 2009: Shoushin Kaikan [Mon, Nov 17], Topics: Embedded System Platform # SECRETARY: Yoshio Hirose (Fujitsu Laboratories Ltd.) TEL 044-754-2783,FAX 044-754-2744 E-mail:y       === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Thu, Dec 18, 2008: KYOTO Research Park [Fri, Oct 31], Topics: Network Storage Systems, etc. Thu, Jan 29, 2009 - Fri, Jan 30, 2009: [Fri, Nov 7] # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:   am  -u=== Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Dec 12, 2008: [Mon, Oct 20] Mon, Feb 16, 2009: [Wed, Dec 10] # SECRETARY: Masato Kitakami Graduate School of Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +42.290.3269 E-mail:   f ultyba-u=== Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Thu, Jan 29, 2009 - Fri, Jan 30, 2009: [Fri, Nov 7] # SECRETARY: Yohei HORI (AIST) E-mail:   yaist TEL: +81-29-861-5080 (Ext.)55459 FAX: +81-29-861-5909 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Thu, Jan 29, 2009 - Fri, Jan 30, 2009: [Fri, Nov 7] # SECRETARY: System LSI Research Center, Kyushu University Tohru ISHIHARA Email: i  slrck shu-uTEL: 092-847-5188 FAX: 092-847-5190 # ANNOUNCEMENT: # Please visit our web site! http://www.ipsj.or.jp/sig/sldm/ Last modified: 2008-11-14 11:44:02 |
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