|
|
| Chair |
|
Noriyuki Minegishi (Mitsubishi Electric) |
| Vice Chair |
|
Nozomu Togawa (Waseda Univ.) |
| Secretary |
|
Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Yutaka Tamiya (Fujitsu Lab.) |
| Secretary |
|
Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.), Eiichi Hosoya (NTT) |
| Assistant |
|
Hiroe Iwasaki (NTT) |
|
| Conference Date |
Wed, May 15, 2019 13:30 - 20:00 |
| Topics |
System Design, etc. |
| Conference Place |
Tokyo Institute of Technology, Ookayama Campus |
| Address |
2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 Japan |
| Transportation Guide |
1-minute walk from Ookayama Station
https://www.titech.ac.jp/english/maps/#ookayama |
| Sponsors |
This conference is supported by IEEE CEDA All Japan Joint Chapter.
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD. |
Wed, May 15 PM
13:30 - 14:45 |
| (1) |
13:30-13:55 |
|
(2)
VLD |
13:55-14:20 |
A study on replica topology and temperature assignment for Ising-Model based Solver via Parallel Tempering  VLD2019-1 |
Akira Dan, Takashi Sato (Kyoto Univ.) |
(3)
VLD |
14:20-14:45 |
Approximate Computing Technique Using Memoization and Simplified Multiplication VLD2019-2 |
Yoshinori Ono, Kimiyoshi Usami (SIT) |
| |
14:45-15:00 |
Break ( 15 min. ) |
Wed, May 15 PM
15:00 - 16:15 |
(4)
VLD |
15:00-15:25 |
Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory VLD2019-3 |
Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
(5)
VLD |
15:25-15:50 |
SRAM-Based Synthesis for Multi-Output Gates VLD2019-4 |
Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) |
(6)
VLD |
15:50-16:15 |
The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process VLD2019-5 |
Hideharu Amano, Hideto Kayashima, Tsunaaki Shidei, Takuya Kojima (Keio Univ.) |
| |
16:15-16:30 |
Break ( 15 min. ) |
Wed, May 15 PM
16:30 - 17:30 |
(7)
VLD |
16:30-17:30 |
[Invited Talk]
Viaswitch FPGA for Energy Efficient Computing VLD2019-6 |
Masanori Hashimoto (Osaka Univ.) |
| |
17:30-18:00 |
Break ( 30 min. ) |
Wed, May 15 PM
18:00 - 20:00 |
| (8) |
18:00-20:00 |
|
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Koyo Nitta (NTT)
E- :  t        |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Yukio Mitsuyama (Kochi Univ. of Tech.)
E-:      o -  |
| Announcement |
Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/ |
Last modified: 2019-05-15 21:16:20
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