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| Chair |
|
Masao Nakaya |
| Vice Chair |
|
Akira Matsuzawa |
| Secretary |
|
Shinji Miyano, Koji Kai |
| Assistant |
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Yoshiharu Aimoto, Makoto Nagata |
|
Thu, Dec 15 AM
10:30 - 13:00 |
| (1) |
10:30-11:20 |
[Special Invited Talk]
Dynamically Reconfigurable Processor DRP and its C based Design Environment |
Toru Awashima (NEC) |
| (2) |
11:20-11:45 |
Scalable Bus Interface for HSDPA Co-processor Extension |
Toshiki Takeuchi, Hiroyuki Igura (NEC), Takeshi Hashimoto (NECEL), Soichi Tsumura, Naoki Nishi (NEC) |
| (3) |
11:45-12:10 |
VLSI Processor Architecture Based on Intra-Chip Packet Data Transfer Scheme (without presentation) |
Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) |
| |
12:10-13:00 |
Lunch ( 50 min. ) |
Thu, Dec 15 PM
13:00 - 15:15 |
| (4) |
13:00-13:50 |
[Special Invited Talk]
Multiprocessor Architecture on Integrated Platform for Digital Consumer Electronics |
Yoshito Nishimichi, Kozo Kimura, Masaitsu Nakajima, Tokuzo Kiyohara (Matsushita Electric) |
| (5) |
13:50-14:15 |
A DVFS Method for High-Performance and Low-Power Chip Multiprocessors |
Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
| (6) |
14:15-14:40 |
Adaptive Instruction Cascading on GALS Microprocessors |
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
| (7) |
14:40-15:05 |
Development of a Special-Purpose Processor for Molecular Orbital Calculations |
Kenta Nakamura, Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
| |
15:05-15:15 |
Break ( 10 min. ) |
Thu, Dec 15 PM
15:15 - 16:55 |
| (8) |
15:15-15:40 |
Evaluation of energy consumption for High-Performance / Low-Leakage Caches based on Always Active line |
Reiko Komiya (Fukuoka Univ.), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
| (9) |
15:40-16:05 |
Performance/Power Analysis of A Secure Cache Architecture for Buffer-Overflow Prevention |
Koji Inoue (Kyushu Univ.) |
| (10) |
16:05-16:55 |
[Special Invited Talk]
Entrepreneur engineering
-- A new concept of engineering education -- |
Osamu Tomisawa, Gota Kano (KUT) |
Fri, Dec 16 AM
09:00 - 10:50 |
| (11) |
09:00-09:25 |
Ultra Small Random Number Generator for Information Security |
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita (Toshiba Corp.) |
| (12) |
09:25-09:50 |
Design of Immune Algorithm Accelerator |
Tsuyoshi Ozeki, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan Univ.) |
| (13) |
09:50-10:15 |
A Low Dynamic Power and Low Leakage Power 90-nm CMOS Clock Driver |
Suguru Nagayama, Tadayoshi Enomoto (Chuo Univ.) |
| (14) |
10:15-10:40 |
Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques |
Muhammad Yazid, Hiroshi Kawaguchi, Takayasu Sakurai (Tokyo Univ.) |
| |
10:40-10:50 |
Break ( 10 min. ) |
Fri, Dec 16 AM
10:50 - 13:00 |
| (15) |
10:50-11:15 |
A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI |
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Masafumi Takahashi, Yukihito Oowaki (Toshiba Corp.) |
| (16) |
11:15-11:40 |
Bootstrap Pass-Transistor Logic with Active Body-Biasing Control on PD-SOI |
Masaaki Iijima, Masayuki Kitamura, Kenji Hamada, Masahiro Numa (Kobe Univ.), Akira Tada, Shigeto Maegawa (Renesas) |
| (17) |
11:40-12:05 |
High Performance CMOS Circuit by using Charge Recycling Actively Body-bias Controlled SOI |
Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa (Kobe Univ.), Hiromi Notani, Akira Tada, Shigeto Maegawa (Renesas) |
| |
12:05-13:00 |
Lunch ( 55 min. ) |
Fri, Dec 16 PM
13:00 - 14:25 |
| (18) |
13:00-13:25 |
Substrate-Coupled Inductor Model for Circuit Design Simulations |
Ivan Chee Hong Lai, Minoru Fujishima (Univ. of Tokyo) |
| (19) |
13:25-13:50 |
200 MSPS Low-Power A-to-D and D-to-A Converters for Next Generation Mobile Communication System |
Daisuke Kurose, Takafumi Yamaji, Takeshi Ueno, Tomohiko Ito, Tetsuro Itakura, Akihide Sai (Toshiba Corp.) |
| (20) |
13:50-14:15 |
A 0.8-1.3V 16-channel 2.5Gbps High-speed Serial Transceiver in a 90nm Standard CMOS Process |
Yoshiyasu Doi (Fujitsu Labs.), Syunitirou Masaki, Takaya Chiba (Fujitsu), Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida (Fujitsu Labs.), Kohtaroh Gotoh (Fujitsu), Junji Ogawa, Hirotaka Tamura (Fujitsu Labs.) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Fri, Dec 16 PM
14:25 - 15:40 |
| (21) |
14:25-14:50 |
A 1.2-V CMOS Complex Bandpass Filter with a Tunable Center Frequency |
Hideaki Majima, Hiroki Ishikuro, Kenichi Agawa, Mototsugu Hamada (Toshiba Corp.) |
| (22) |
14:50-15:15 |
A UWB Impulse-radio Transmitter with Digitally-controlled Pulse Generator |
Takayasu Norimatsu, Ryosuke Fujiwara, Masaru Kokubo, Masayuki Miyazaki (Hitachi), Yasuyuki Okuma, Miki Hayakawa, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura (YRP UNL) |
| (23) |
15:15-15:40 |
Variable Gain Amplifier in Polar Loop Modulation Transmitter for EDGE |
Masahiro Ito, Taizo Yamawaki (Hitachi, Ltd.), Masumi Kasahara (Renesas Technology Corp.), Steve Williams (TTPCom Limited) |
| Announcement for Speakers |
| General Talk (25) | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Special Invited Talk (50) | Each speech will have 40 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Makoto Nagata (Kobe Univ.)
TEL: 078-803-6569 FAX: 078-803-6221
E- :        be-u |
Last modified: 2005-11-02 13:40:57
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