Thu, Aug 23 AM  08:30 - 10:10
(1)	08:30-08:55	Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors SDM2007-141 ICD2007-69	Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas)
(2)	08:55-09:20	Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC SDM2007-142 ICD2007-70	Tetsu Hosoki, Takao Yamamoto, Masayuki Yamasaki, Keisuke Kaneko, Masaitsu Nakajima (Matsushita Electric Industrial Co., Ltd.)
(3)	09:20-09:45	Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding SDM2007-143 ICD2007-71	Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
(4)	09:45-10:10	Fast Motion Estimation Algorithm and a Low Power Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling SDM2007-144 ICD2007-72	Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
	10:10-10:20	Break ( 10 min. )
Thu, Aug 23 AM  10:20 - 12:00
(5)	10:20-11:10	[Special Invited Talk] Design Trends of High Performance PLLs and DLLs SDM2007-145 ICD2007-73	Shiro Dosho (Matsushita)
(6)	11:10-11:35	Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application SDM2007-146 ICD2007-74	Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho (Matsushita)
(7)	11:35-12:00	A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms SDM2007-147 ICD2007-75	Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro (NEC)
	12:00-12:50	Lunch Break ( 50 min. )
Thu, Aug 23 PM  12:50 - 14:30
(8)	12:50-13:40	[Special Invited Talk] Past and Future of Dynamic Voltage Scaling SDM2007-148 ICD2007-76	Hiroyuki Mizuno (Hitachi)
(9)	13:40-14:05	Energy comparison between various supply voltage scheme for System LSI SDM2007-149 ICD2007-77	Satoshi Hanami, Shigeyoshi Watanabe, Manabu Kobayashi, Toshinori Takabatake (SIT)
(10)	14:05-14:30	Design of high-speed low-power dual-supply-voltage sysytem LSI taking into account of gate/sub-threshold leakage current SDM2007-150 ICD2007-78	Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT)
	14:30-14:35	Break ( 5 min. )
Thu, Aug 23 PM  14:35 - 15:50
(11)	14:35-15:00	An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations SDM2007-151 ICD2007-79	Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara (NEC Corp.)
(12)	15:00-15:25	Power Measurement for a Multiplier with Run Time Power Gating SDM2007-152 ICD2007-80	Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T)
(13)	15:25-15:50	A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors SDM2007-153 ICD2007-81	Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology)
	15:50-16:00	Break ( 10 min. )
Thu, Aug 23 PM  16:00 - 18:00
(14)	16:00-18:00	[Panel Discussion] Dynamic Voltage & Frequency Scaling ; A Key Technology for Deep Sub-100nm SoCs ! SDM2007-154 ICD2007-82	Tadayoshi Enomoto (Chuo Univ.), Naohiko Irie (Hitachi), Hiroshi Okano (Fujitsu), Shiro Sakiyama (Matsushita), Masakatsu Nakai (Sony), Koji Nii (Renesas Technology), Masahiro Nomura (NEC), Hiroyuki Mizuno (Hitachi)
Fri, Aug 24 AM  08:30 - 10:10
(1)	08:30-08:55	A Very Wideband Fully Balanced Active RC Polyphase Filter Based on CMOS Inverters in 0.18μm CMOS Technology SDM2007-155 ICD2007-83	Keishi Komoriyama, Eiich Yoshida, Makoto Yashiki, Hiroshi Tanimoto (Kitami Inst. Tech.)
(2)	08:55-09:20	Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variation in SoCs SDM2007-156 ICD2007-84	Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura (Kobe Univ.), Rei Akiyama (Renesas Design), Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata (Renesas Technology), Makoto Nagata (Kobe Univ.)
(3)	09:20-09:45	An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise SDM2007-157 ICD2007-85	Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo)
(4)	09:45-10:10	A Microwave-Powered CMOS Power Supply Circuit for Integrated Si-MEMS Microsensors SDM2007-158 ICD2007-86	Daiki Endo (TUT), Hidekuni Takao (TUT/JST-CREST), Syunsuke Kizuna (TUT), Kazuaki Sawada, Makoto Ishida (TUT/JST-CREST)
	10:10-10:20	Break ( 10 min. )
Fri, Aug 24 AM  10:20 - 12:00
(5)	10:20-11:10	[Special Invited Talk] Effect of metal-gate/high-k on characteristics of MOSFETs for 32nm CMOS and beyond SDM2007-159 ICD2007-87	Masato Koyama, Masahiro Koike, Yuuichi Kamimuta, Masamichi Suzuki, Kosuke Tatsumura, Yoshinori Tsuchiya, Reika Ichihara, Masakazu Goto, Koji Nagatomo, Atsushi Azuma, Shigeru Kawanaka, Kazuaki Nakajima, Katsuyuki Sekine (Toshiba Corp.)
(6)	11:10-11:35	Experimental Study on Mobility Universality in (100) Ultra Thin Body nMOSFET with SOI thickness of 5 nm SDM2007-160 ICD2007-88	Ken Shimizu, Toshiro Hiramoto (Univ. of Tokyo)
(7)	11:35-12:00	An analysis of asymmetry and orientation dependence of n-MOSFETs SDM2007-161 ICD2007-89	Toshihiro Matsuda, Yuya Sugiyama, Hideyuki Iwata (Toyama Pref. Univ.), Takashi Ohzone (Okayama Pref. Univ.)
	12:00-13:00	Lunch Break ( 60 min. )
Fri, Aug 24 PM  13:00 - 14:40
(8)	13:00-13:50	[Special Invited Talk] Towards Great Nanoelectronics Country, Japan SDM2007-162 ICD2007-90	Hisatsune Watanabe (Selete)
(9)	13:50-14:15	Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of Pattern Area Reduction with CMOS Cell Library -- SDM2007-163 ICD2007-91	Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT)
(10)	14:15-14:40	Ｄesign Method of system LSI with FinFET type DTMOS SDM2007-164 ICD2007-92	Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT)
	14:40-14:50	Break ( 10 min. )
Fri, Aug 24 PM  14:50 - 16:55
(11)	14:50-15:15	0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node SDM2007-165 ICD2007-93	Hiroyuki Onoda, Katsura Miyashita, Takeo Nakayama, Tomoko Kinoshita, Hisashi Nishimura, Atsushi Azuma, Seiji Yamada, Fumitomo Matsuoka (Toshiba)
(12)	15:15-15:40	SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for suppressing read disturbance and write-current dispersion SDM2007-166 ICD2007-94	Katsuya Miura, Takayuki Kawahara, Riichiro Takemura (Hitachi, Ltd.), Jun Hayakawa (Hitachi, Ltd./Tohoku Univ.), Michihiko Yamanouchi (Hitachi, Ltd.), Shoji Ikeda, Ryutaro Sasaki (Tohoku Univ.), Kenchi Ito, Hiromasa Takahashi, Hideyuki Matsuoka (Hitachi, Ltd.), Hideo Ohno (Tohoku Univ.)
(13)	15:40-16:05	An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment SDM2007-167 ICD2007-95	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
(14)	16:05-16:30	A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues SDM2007-168 ICD2007-96	Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial)
(15)	16:30-16:55	A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology SDM2007-169 ICD2007-97	Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.)

Contact Address and Latest Schedule Information
SDM	Technical Committee on Silicon Device and Materials (SDM)   [Latest Schedule]
	Contact Address	Shigeru Kawanaka (Semiconductor Company, Toshiba) TEL 045-770-3642, FAX 045-776-4104 E-：geba
ICD	Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
	Contact Address	Yoshiharu Aimoto (NEC Electronics Corporation) TEL +81-44-435-1258, +81-44-435-1878 E-:aicel

Last modified: 2007-07-04 16:49:57