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Technical Committee on VLSI Design Technologies (VLD)
Chair: Hirofumi Hamamura Vice Chair: Nagisa Ishiura
Secretary: Toshiyuki Shibuya, Hiroyuki Ochi

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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Masao Nakaya Vice Chair: Akira Matsuzawa
Secretary: Koji Kai, Yoshiharu Aimoto
Assistant: Makoto Nagata, Minoru Fujishima

DATE:
Wed, Mar 7, 2007 13:00 - 18:00
Thu, Mar 8, 2007 08:30 - 18:00
Fri, Mar 9, 2007 08:40 - 17:00

PLACE:
Mielparque-Okinawa(20, Aza-Matsukawa, Naha, 902-0062. http://www.mielparque.or.jp/okn/eng.html)

TOPICS:
System-on-silicon design techniques and related VLSs

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Wed, Mar 7 PM (13:00 - 14:40)
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(1) 13:00 - 13:20
Multi-Port Filters Using On-Chip Transmission Lines for Millimeter-Wave CMOS
Naoki Kobayashi, Minoru Fujishima (The Univ. Tokyo)

(2) 13:20 - 13:40
A Scalable Model of Shielded Capacitors using Mirror Image Effects
Koji Ishibashi, Minoru Fujishima (The Univ. Tokyo)

(3) 13:40 - 14:00
Partially-parallel decoder based on high-efficiency message-passing schedule for irregular LDPC code
Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)

(4) 14:00 - 14:20
Fast Motion Estimation Algorithm Employing Adaptively Assigned Stopping Condition
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

(5) 14:20 - 14:40
A 90-nm CMOS Motion Estimation Processor for MPEG4 implementing Dynamic Voltage and Frequency Scaling
Yuhgo Ishikawa, Tatsuya Kaneko, Takeshi Iwanari, Hiroaki Nakayama, Toshihiro Tsutusi, Yousuke Hagiwara, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

----- Break ( 20 min. ) -----

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Wed, Mar 7 PM Front-End Design (1) (15:00 - 16:20)
Chair: Kazunori Shimizu (Waseda Univ.)
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(6) 15:00 - 15:20
Hardware/Software Automatic Partitioning using Behavioral Synthesis
Daisuke Iwama, Naoto Miyamoto, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ.)

(7) 15:20 - 15:40
Design Checker for System-Level Design using Extended System Dependence Graph
Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo)

(8) 15:40 - 16:00
Specification description and verification methods for IPs of hardware design
Yuji Ishikawa (Univ. of Tokyo), SeongWoon Kang (Samsung), Yeonbok Lee (Univ. of Tokyo), GiLark Park (Samsung), Shota Watanabe, Kenshu Seto, Satoshi Komatsu (Univ. of Tokyo), Hirofumi Hamamura (Samsung), Masahiro Fujita (Univ. of Tokyo)

(9) 16:00 - 16:20
IP library retrieval system for design reuse
Yeonbok Lee (University of Tokyo), GiLark Park (SAMSUNG), Yuji Ishikawa (University of Tokyo), SeongWoon Kang (SAMSUNG), Shota Watanabe, Kenshu Seto, Satoshi Komatsu (University of Tokyo), Hirofumi Hamamura (SAMSUNG), Masahiro Fujita (University of Tokyo)

----- Break ( 20 min. ) -----

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Wed, Mar 7 PM (16:40 - 18:00)
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(10) 16:40 - 17:00
Equivalent Circuit Modeling of Guard Ring Structures for Evaluation of Substrate Crosstalk Isolation
Daisuke Kosaka, Makoto Nagata (Kobe Univ.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec)

(11) 17:00 - 17:20
On-chip monitoring for sub-100-nm digital signal integrity
Yoji Bando, Koichiro Noguchi, Makoto Nagata (Kobe Univ.)

(12) 17:20 - 17:40
A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits
Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)

(13) 17:40 - 18:00
A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yuan Yang (Xi’an Univ. of Technology), Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)

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Thu, Mar 8 AM Processor Synthesis/High-Level Synthesis (08:30 - 10:10)
Chair: Satoshi Komatsu (Univ. of Tokyo)
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(14) 08:30 - 08:50
A Processing Unit Optimization Algorithm in SIMD Processor Cores Design
Hiroyuki Shigeta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

(15) 08:50 - 09:10
A Hardware/Software Partitioning Framework for SIMD Processor Cores
Masataka Ohigashi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

(16) 09:10 - 09:30
SIMD Instructions Generation Algorithm for Multiple Loop for SIMD Processor Cores Optimum Design
Hiroki Nakajima, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

(17) 09:30 - 09:50
An Application Specific Data Optimization System for Processor Cores and Its Experimental Evaluation
Kazuhisa Horiuchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

(18) 09:50 - 10:10
An efficient design methodology for image processing digital system by using a high level hardware description language
Satoru Inoue, Taiki Hashizume, Tomonori Izumi, Masahiro Fukui (Ritsumeikan Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Thu, Mar 8 AM (10:30 - 12:10)
----------------------------------------

(19) 10:30 - 10:50
Mixed Analog-Digital Fully-Parallel Associative Memory with Search
Yuki Tanaka, Md. Anwarul Abedin, Tetsushi Koide, Mattausch. Hans Juergen (Hiroshima Univ.)

(20) 10:50 - 11:10
A 90-nm SRAM for Video Signal Processors implementing Dynamic Voltage and Frequency Scaling
Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

(21) 11:10 - 11:30
A Clock Deskew Method Using Statisical Presumption
Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC)

(22) 11:30 - 11:50
A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits
Yousuke Harada, Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech.)

(23) 11:50 - 12:10
Low Power and High Speed Clock Distribution Technique for 90-nm CMOS LSIs
Yousuke Hagiwara, Suguru Nagayama, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

----- Lunch Break ( 60 min. ) -----

----------------------------------------
Thu, Mar 8 PM Placement and Routing (13:10 - 14:50)
Chair: Tomonori IZUMI (Ritsumeikan Univ.)
----------------------------------------

(24) 13:10 - 13:30
The Potential Router
Yoji Kajitani (Univ. of Kitakyushu)

(25) 13:30 - 13:50
Escape Fitting between a Pair of Pin-Sets
Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu)

(26) 13:50 - 14:10
BGA Routing by The Potential Router
Takayuki Hiromatsu, Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu)

(27) 14:10 - 14:30
Automatic routing methods which make modification after routing easy
Toshihiko Yokomaru, Takahide Yoshikawa, Yuzi Kanazawa (Fujitsu Labs.)

(28) 14:30 - 14:50
Relocation Method for Circuit Modification
Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)

----- Break ( 20 min. ) -----

----------------------------------------
Thu, Mar 8 PM Reconfigurable Device/Calibration (15:10 - 16:50)
Chair: Masanori Muroyama (Kyushu Univ.)
----------------------------------------

(29) 15:10 - 15:30
A CAM Emulator Using Look-Up Table Cascades
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)

(30) 15:30 - 15:50
Design Method of Radix Converters Using Arithmetic Decompositions (3)
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.)

(31) 15:50 - 16:10
Design of RSA Encryption circuit with embedded Fixed Private Key using Via Programmable Logic VPEX
Hiroshi Shimomura, Kazuki Okuyama, Akihiro Nakamura, Takeshi Fujino (Ritsumei Univ.)

(32) 16:10 - 16:30
Programmable CMOS Analog Circuit with Body Biasing
Youhei Ide, Toru Fujimura, Shinya Takeshita, Masatoshi Nakamura, Shigetoshi Nakatake (Univ. of Kitakyushu)

(33) 16:30 - 16:50
Novel fast digital background calibration for pipelined ADC's
Takashi Oshima (Hitachi), Cheonguyrn Tsang, Cheonguyrn Tsang (UC Berkeley)

----- Break ( 20 min. ) -----

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Thu, Mar 8 PM (17:10 - 18:00)
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(34) 17:10 - 18:00
[Invited Talk]
Measurements and reduction of power line noises in SoCs
Makoto Ikeda, Kunihiro Asada (Tokyo Univ.)

----- ( 120 min. ) -----

----------------------------------------
Fri, Mar 9 AM Arithmetic Circuits/Special-Purpose Circuits (08:40 - 10:40)
Chair: Hiroyuki Ochi (Kyoto Univ.)
----------------------------------------

(35) 08:40 - 09:00
Easily Testable Multiplier with 4-2 Adder Tree
Nobutaka Kito, Kensuke Hanai, Naofumi Takagi (Nagoya Univ.)

(36) 09:00 - 09:20
Effect of the Number of Wiring Layers on the Chip Area of Multipliers
Hirotaka Kawashima, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.)

(37) 09:20 - 09:40
A Combined Circuit for Multiplication and Inversion in GF(2^m) Based on the Extended Euclid's Algorithm
Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ.)

(38) 09:40 - 10:00
A Study of Fast Projective Transformation Method
Yoshinori Yamada, Yasuhide Kimura, Daisuke Itou, Tomoyuki Yokogawa, Yoichiro Sato, Michiyoshi Hayase (Okayama Prefectural Univ.)

(39) 10:00 - 10:20
On an Optimality of a Sampling Circuit for Liquid Crystal Displays
Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.), Masanori Hashimoto (Osaka Univ.), Isao Shirakawa (University of Hyogo)

(40) 10:20 - 10:40
A Consideration of MPEG-A Photo Player Meta-data Generation System Design with Hardware Acceleration for Mobile Devices
Masato Motohashi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Fri, Mar 9 AM (11:00 - 11:50)
----------------------------------------

(41) 11:00 - 11:50
[Invited Talk]
System LSI Architecture for Embedded Applications in Multi-Core era
Naohiko Irie (Hitachi, CRL)

----- Lunch Break ( 70 min. ) -----

----------------------------------------
Fri, Mar 9 PM Front-End Design (2) (13:00 - 15:00)
Chair: Makoto Nagata (Kobe Univ.)
----------------------------------------

(42) 13:00 - 13:20
An Object Oriented System LSI Design Method Using Java Language
Seigo Masuoka, Hiroyuki Terai, Manabu Koyama (Kinki Univ.), Kazuhiko Nakahara (Spansion Japan), Akihisa Yamada (Sharp), Takashi Kambe (Kinki Univ.)

(43) 13:20 - 13:40
A method to evaluate logic function by using decision diagram with memory packing.
Hiroyuki Tanaka, Hiroki Nakahara, Munehiro Matsuura, Tsutomu Sasao (KIT)

(44) 13:40 - 14:00
Design Method of High Density System LSI with Three-Dimensional Transistor (FinFET)
-- Pattern Area Reduction of System LSI --
Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (Shonan Institute of Tech.)

(45) 14:00 - 14:20
A Study of Performance Evaluation on Globally Asynchronous Locally Synchronous Systems
Kazuyuki Tashiro, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Isao Kayano (Kawasaki College of Allied Health Professions), Yoichiro Sato, Michiyoshi Hayase (Okayama Prefectural Univ.)

(46) 14:20 - 14:40
A behavioral power modeling algorithm which considers area speed tradeoff
Noriyuki Inoue, Masaaki Ohtsuki, Masahiro Fukui (Ritsumeikan Uni.)

(47) 14:40 - 15:00
An efficient battery modeling and optimization for battery driven systems
Sayaka Iwakoshi, Yu Chikayama, Masahiro Fukui (Ritsumeikan Univ.)

----- Break ( 20 min. ) -----

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Fri, Mar 9 PM (15:20 - 17:00)
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(48) 15:20 - 15:40
Design method of low-power dual-supply-voltage system LSI taking into account gate/subthreshold leakage current of MOSFET
Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (Shonan Institute of Tech.)

(49) 15:40 - 16:00
Analysis for factors that affect power dissipation for Multiplier applying Run Time Power Gating
Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T.)

(50) 16:00 - 16:20
Characteristic of Random Curved Surface and a Proposition of a New Curved Surface Model
-- An Universal Random Curved Surface Model Formed from Rotational Gaussians --
Shin-ichi Ohkawa, Hiroo Masuda (Renesas)

(51) 16:20 - 16:40
Statistical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations
Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya (Fujitsu Labs.)

(52) 16:40 - 17:00
Sequence-Pair Based Compaction under Crosstalk Constraint
Tetsuya Tashiro, Takehiko Matsuo, Shigetoshi Nakatake (Univ. of Kitakyushu)

# Information for speakers
General Talk will have 15 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Thu, May 10, 2007 - Fri, May 11, 2007: Kyodai Kaikan [Thu, Mar 15], Topics: System Design, etc.
Thu, Jun 21, 2007 - Fri, Jun 22, 2007: Hokkaido Tokai Univ. (Sapporo) [Fri, Apr 13]

# SECRETARY:
Shibuya Toshiyuki(Fujitsu Laboratories)
E-mail:bu
Tel.044-754-2663

# ANNOUNCEMENT:
# You will see the latest information at the below WEB page.
http://www.ieice.org/~vld/

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, May 31, 2007 - Fri, Jun 1, 2007: [Fri, Mar 23], Topics: Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC

# SECRETARY:
Koji Inoue (Kyushu University)
TEL +81-92-802-3793,FAX +81-92-802-3786
E-mail:iikshu-u


Last modified: 2007-02-21 18:55:36


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