IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

===============================================
Technical Committee on VLSI Design Technologies (VLD)
Chair: Toshiyuki Shibuya (Fujitsu Labs.) Vice Chair: Yusuke Matsunaga (Kyushu Univ.)
Secretary: Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.)
Assistant: Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric)

===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Masahiro Fukui (Ritsumeikan Univ.)
Secretary: Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.), Masao Yokoyama (Sharp)

DATE:
Thu, May 14, 2015 09:15 - 15:50

PLACE:
Kitakyushu International Conference Center(Prof. Shigetoshi Nakatake)

TOPICS:
System Design, etc.

----------------------------------------
Thu, May 14 AM (09:15 - 10:30)
----------------------------------------

(1)/VLD 09:15 - 09:40
A minimum test pattern set generation for large circuits
Yusuke Matsunaga (Kyushu Univ.)

(2)/VLD 09:40 - 10:05
Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement
Hiroyuki Iwasaki, Hiroshi Miyashita (The Univ. of Kitakyushu)

(3)/VLD 10:05 - 10:30
NP-completeness of Routing Problem with Bend Constraint
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech)

----- Break ( 15 min. ) -----

----------------------------------------
Thu, May 14 AM (10:45 - 12:00)
----------------------------------------

(4) 10:45 - 11:10


(5) 11:10 - 11:35


(6)/VLD 11:35 - 12:00
Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits
Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)

----- Lunch ( 80 min. ) -----

----------------------------------------
Thu, May 14 PM (13:20 - 14:20)
----------------------------------------

(7)/VLD 13:20 - 14:20
[Invited Talk]
Trends and Future Challenges of Nano-electronics R&D in Japan
Seiichiro Kawamura (JST)

----- Break ( 15 min. ) -----

----------------------------------------
Thu, May 14 PM (14:35 - 15:50)
----------------------------------------

(8) 14:35 - 15:00


(9)/VLD 15:00 - 15:25
Power Analysis Method for a Lightweight Block Cipher Simon
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)

(10)/VLD 15:25 - 15:50
AES Encryption Circuit against Clock Glitch based Fault Analysis
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.


=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Wed, Jun 17, 2015 - Thu, Jun 18, 2015: Otaru University of Commerce [Thu, Apr 16], Topics: System, signal processing and related topics
Mon, Aug 10, 2015 - Tue, Aug 11, 2015: Ho Chi Minh city University of Sciences (HCMUS) [Tue, Jun 30], Topics: The 6th International Conference on Integrated Circuits, Design, and Verification (ICDV 2015)

# SECRETARY:
Noriyuki Minegishi (Mitsubishi Electric Corporation)
E-mail: minegishi.noriyuki@aj.mitsubishielectric.co.jp
Tel: 0467-41-2944

# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/

=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===

# SECRETARY:
Makoto Sugihara (Kyushu University)
Email sldm2013@soc.ait.kyushu-u.ac.jp

# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2015-04-24 16:01:43


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to VLD Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan