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=============================================== Technical Committee on Silicon Device and Materials (SDM) Chair: Tanemasa Asano Vice Chair: Toshihiro Sugii Secretary: Morifumi Ohno, Shigeru Kawanaka Assistant: Yuichi Matsui =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Masao Nakaya Vice Chair: Akira Matsuzawa Secretary: Koji Kai, Yoshiharu Aimoto Assistant: Makoto Nagata, Minoru Fujishima DATE: Thu, Aug 17, 2006 09:05 - 17:50 Fri, Aug 18, 2006 09:00 - 17:30 PLACE: Hokkaido University(Kita-8-Jo, Nishi-5-chome, Kita-ku, Sapporo-shi, 060-0808 Japan.http://www.hokudai.ac.jp/footer/ft_access.html, http://www.hokudai.ac.jp/bureau/gaiyou/2005/p37.htm. Tetsuya Hirose) TOPICS: ---------------------------------------- Thu, Aug 17 AM (09:05 - 10:45) ---------------------------------------- (1) 09:05 - 09:30 A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) (2) 09:30 - 09:55 A 0.79mm2 29mW Real-Time Face Detection Core Yuichi Hori, Tadahiro Kuroda (Keio Univ.) (3) 09:55 - 10:20 A supply voltage adjustment technique for low power consumption and its application to SOCs with multiple threshold voltage CMOS Hiroshi Okano, Tetsuyoshi Shiota, Yukihito Kawabe (Fujitsu lab.), Wataru Shibamoto (Fujitsu), Tetsutaro Hashimoto, Atsuki Inoue (Fujitsu lab.) (4) 10:20 - 10:45 Low power delay-insensitive asynchronous curcuits using 1-out-of-4 encoding. Tomohiro Fujii, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Aug 17 AM (10:55 - 12:35) ---------------------------------------- (5) 10:55 - 11:20 A 1-ps resolution on-chip sampling oscilloscope with 64:1 tunable sampling range based on ramp waveform division scheme Kenichi Inagaki (Univ. of Tokyo), Danardono Dwi Antono (SONY), Makoto Takamiya (Univ. of Tokyo), Shigetaka Kumashiro (NEC Electronics), Takayasu Sakurai (Univ. of Tokyo) (6) 11:20 - 11:45 A CMOS Monitoring Sensor for Guaranteeing the Quality of Various Perishables with a Wide Range of Activation Energy Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) (7) 11:45 - 12:10 Critical temperature switch circuit with CMOS subthreshold region Atsushi Hagiwara, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) (8) 12:10 - 12:35 Ultra Low-Power Low-noise Amplifier Using The MOS Capacitor Amplifier Tomotoshi Murakami, Mamoru Sasaki, Atsushi Iwata (Hiroshima Univ.) ----- Lunch ( 55 min. ) ----- ---------------------------------------- Thu, Aug 17 PM (13:30 - 15:35) ---------------------------------------- (9) 13:30 - 14:20 [Special Invited Talk] Development of SOI-Based 7.5μm-Thick 0.15x0.15mm2 RFID Chip Mitsuo Usami (Hitachi) (10) 14:20 - 14:45 Analysis of Junction Capacitance effect in Dickson Charge Pump for RF-ID Yasufumi Sakai, Koji Kotani, Takashi Ito (Tohoku Univ.) (11) 14:45 - 15:10 A 1-V 299uW Flashing UWB Transceiver Based on Double Thresholding Scheme Makoto Takamiya, Atit Tamtrakarn (Univ. of Tokyo), Hiroki Ishikuro (Keio Univ.), Koichi Ishida (Tokyo Tech), Takayasu Sakurai (Univ. of Tokyo) (12) 15:10 - 15:35 Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link Mari Inoue, Noriyuki Miura, Kiichi Niitsu (Keio Univ.), Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi (NEC Corp.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Aug 17 PM (15:45 - 17:50) ---------------------------------------- (13) 15:45 - 16:10 Noncontact serial transmission system using inductive coupling of spiral inductor pair Bin Yan, Mamoru Sasaki, Atsushi Iwata (Hiroshima Univ.) (14) 16:10 - 16:35 A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range Takayuki Shibasaki (Keio Univ.), Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa (Fujitsu Laboratories LTD.), Tadahiro Kuroda (Keio Univ.) (15) 16:35 - 17:00 17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator Atsushi Mori, Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Iwata (Hiroshima Univ.), Hiroaki Ikeda (Elpida) (16) 17:00 - 17:25 Low Dynamic Power and High Speed 90-nm CMOS Clock Driver Yousuke Hagiwara, Suguru Nagayama, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Uni.) (17) 17:25 - 17:50 An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie (Matsushita Indusitrial Co. Ltd.) ---------------------------------------- Fri, Aug 18 AM (09:00 - 10:40) ---------------------------------------- (18) 09:00 - 09:25 A Test Structure to Separately Analyze CMOSFET Reliabilities along The Channel Width Takashi Ohzone, Eiji Ishii, Takayuki Morishita, Kiyotaka Komoku (Okayama Pref. Univ.), Toshihiro Matsuda, Hideyuki Iwata (Toyama Pref. Univ.) (19) 09:25 - 09:50 Experimental Study on Breakdown of Mobility Universality in (110)-oriented <100>-directed pMOSFETs Ken Shimizu, Takuya Saraya, Toshiro Hiramoto (Univ. of Tokyo) (20) 09:50 - 10:15 Parameter and Random Dopant Fluctuation on Fully-Depleted SOI MOSFETs with a Very Thin BOX Tetsu Ohtou (Univ. Tokyo), Nobuyuki Sugii (R&D Group, Hitachi, Ltd.,), Toshiro Hiramoto (Univ. Tokyo) (21) 10:15 - 10:40 Suppression effects of threshold voltage variation with Ni FUSI gate electrode for 45nm node and beyond LSTP and SRAM devices Yasunori Okayama, Tomohiro Saito, Aname Oishi, Kazuaki Nakajima, Kouji Matsuo, Syuichi Taniguchi, Takatoshi Ono, Kazuhiro Nakayama, Ryota Watanabe, Ayumi Eiho, Taiki Komoda, Taiki Kimura, Mssahumi Hamaguchi, Yoichi Takekawa, Tomonori Aoyama (TOSHIBA) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Aug 18 AM (10:50 - 12:55) ---------------------------------------- (22) 10:50 - 11:40 [Special Invited Talk] High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology Shinpei Yamaguchi, Kaori Tai, Tomoyuki Hirano, Takshi Ando, Susumu Hiyama, Junli Wang, Yoshiya Hagimoto, Yoshihiko Nagahama, Takayoshi Kato, Kaori Nagano, Mayumi Yamanaka, Sanae Terauchi, Saori Kanda, Ryo Yamamoto, Ｙａｓｕｓｈｉ Tateshita (STDG, SONY Corp.) (23) 11:40 - 12:05 Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond Hirohisa Kawasaki (TAEC), Satoshi Inaba, Kimitoshi Okano, Akio Kaneko (Toshiba Semicon.), Atsushi Yagishita (TAEC), Takashi Izumida, Takahisa Kanemura, Takahiko Sasaki, Nobuaki Otsuka, Nobutoshi Aoki, Kyoichi Suguro, Kazuhiro Eguchi, Yoshitaka Tsunashima (Toshiba Semicon.), Kazunari Ishimaru (TAEC), Hidemi Ishiuchi (Toshiba Semicon.) (24) 12:05 - 12:30 A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) (25) 12:30 - 12:55 A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses Toshikazu Suzuki (Matsushita), Hiroyuki Yamauchi (Fukuoka Institute of Technology Univ.), Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu (Matsushita) ----- Lunch ( 50 min. ) ----- ---------------------------------------- Fri, Aug 18 PM (13:45 - 15:50) ---------------------------------------- (26) 13:45 - 14:35 [Special Invited Talk] Deep Pipelined SRAM Design for High Performance Processor Toru Asano (IBM Japan) (27) 14:35 - 15:00 A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) (28) 15:00 - 15:25 A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment Hiroki Noguchi (Kobe Univ.), Yasuhiro Morita (Kanazawa Univ.), Hidehiro Fujiwara, Kentaro Kawakami, Junichi Miyakoshi (Kobe Univ.), Shinji Mikami (Kanazawa Univ.), Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) (29) 15:25 - 15:50 Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Aug 18 PM (16:00 - 17:30) ---------------------------------------- (30) 16:00 - 17:30 # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. Invited Talk will have 40 minutes for presentation and 10 minutes for discussion. # CONFERENCE SPONSORS: - IEEE SSCS Japan Chapter === Technical Committee on Silicon Device and Materials (SDM) === # FUTURE SCHEDULE: Mon, Sep 25, 2006 - Tue, Sep 26, 2006: Kikai-Shinko-Kaikan Bldg. [Fri, Jul 14], Topics: Process, Device, Circuit Simulation, etc. Fri, Nov 24, 2006: Central Electric Club [Fri, Sep 15] # SECRETARY: Shigeru Kawanaka (Toshiba Semiconductor Company) TEL:045-770-3638, FAX:045-770-3571 E-mail:  ge       ba === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Thu, Oct 26, 2006 - Fri, Oct 27, 2006: [Fri, Aug 18] # SECRETARY: Makoto Nagata (Kobe University) TEL 078-803-6569,FAX 078-803-6221 E-mail:     be-u Last modified: 2006-07-21 21:30:36 |
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